From 6883a43680c4619dd02e89b1d74a6133212fe31f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 20 Nov 2019 19:36:51 +0100 Subject: [PATCH] soc/cores/clock: change drp_locked to CSRStatus and connect it :) --- litex/soc/cores/clock.py | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py index e1964555..5d3ce6ec 100644 --- a/litex/soc/cores/clock.py +++ b/litex/soc/cores/clock.py @@ -91,14 +91,14 @@ class XilinxClocking(Module, AutoCSR): raise ValueError("No PLL config found") def expose_drp(self): - self.drp_reset = CSR() - self.drp_locked = CSR() - self.drp_read = CSR() - self.drp_write = CSR() - self.drp_drdy = CSRStatus() - self.drp_adr = CSRStorage(7) - self.drp_dat_w = CSRStorage(16) - self.drp_dat_r = CSRStatus(16) + self.drp_reset = CSR() + self.drp_locked = CSRStatus() + self.drp_read = CSR() + self.drp_write = CSR() + self.drp_drdy = CSRStatus() + self.drp_adr = CSRStorage(7) + self.drp_dat_w = CSRStorage(16) + self.drp_dat_r = CSRStatus(16) # # # @@ -119,6 +119,7 @@ class XilinxClocking(Module, AutoCSR): self.drp_drdy.status.eq(1) ) ] + self.comb += self.drp_locked.status.eq(self.locked) def do_finalize(self): assert hasattr(self, "clkin") -- 2.30.2