From 68b865650bc4acdd8ec2f0a7454d1fcd0de3f584 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 3 Jun 2018 01:29:43 +0100 Subject: [PATCH] add downsides slide --- simple_v_extension/simple_v_chennai_2018.tex | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index b05ff6497..0a5b56a90 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -405,6 +405,21 @@ for (int i = 0; i < VL; ++i) } +\frame{\frametitle{What's the downside(s) of SV?} + \begin{itemize} + \item EVERY register operation is inherently parallelised\\ + (scalar ops are just vectors of length 1) + \item An extra pipeline phase is pretty much essential\\ + for fast low-latency implementations + \item Assuming an instruction FIFO, N ops could be taken off\\ + of a parallel op per cycle (avoids filling entire FIFO;\\ + also is less work per cycle: lower complexity / latency) + \item With zeroing off, skipping non-predicated elements is hard:\\ + it is however an optimisation (and could be skipped). + \end{itemize} +} + + \frame{\frametitle{Is this OK (low latency)? Detect scalar-ops (only)} \begin{center} \includegraphics[height=2.5in]{scalardetect.png}\\ -- 2.30.2