From 68d125f3ccf46722792d7f56cf55861ec70759fd Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 3 Nov 2020 13:53:41 +0000 Subject: [PATCH] swap jtag pinorder to match ulx3s --- src/soc/litex/florent/versa_ecp5.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/litex/florent/versa_ecp5.py b/src/soc/litex/florent/versa_ecp5.py index 75e33bc2..464e9412 100755 --- a/src/soc/litex/florent/versa_ecp5.py +++ b/src/soc/litex/florent/versa_ecp5.py @@ -43,9 +43,9 @@ class VersaECP5TestSoC(versa_ecp5.BaseSoC): # define the pins, add as an extension, *then* request it jtag_ios = [ ("jtag", 0, - Subsignal("tck", Pins("B19"), IOStandard("LVCMOS25")), + Subsignal("tdi", Pins("B19"), IOStandard("LVCMOS25")), Subsignal("tms", Pins("B12"), IOStandard("LVCMOS25")), - Subsignal("tdi", Pins("B9"), IOStandard("LVCMOS25")), + Subsignal("tck", Pins("B9"), IOStandard("LVCMOS25")), Subsignal("tdo", Pins("E6"), IOStandard("LVCMOS25")), ) ] -- 2.30.2