From 69351dfa6d2a62c46167728832e0411b28a20bd4 Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Jun 2021 15:48:14 +0100
Subject: [PATCH] no, do not assign clock to clock!

---
 src/soc/litex/florent    | 2 +-
 src/soc/simple/issuer.py | 2 --
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/soc/litex/florent b/src/soc/litex/florent
index c709ad7d..d7e76c5b 160000
--- a/src/soc/litex/florent
+++ b/src/soc/litex/florent
@@ -1 +1 @@
-Subproject commit c709ad7d10143a32d9b36e4262f92da989035527
+Subproject commit d7e76c5ba83b12e8466f16294ad052b62f679ce1
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0cc7f428..4f559ce1 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1299,10 +1299,8 @@ class TestIssuer(Elaboratable):
         # XXX BYPASS PLL XXX
         if False and self.pll_en:
             comb += intclk.eq(pllclk)
-            comb += dbgclk.eq(pllclk)
         else:
             comb += intclk.eq(ClockSignal())
-            comb += dbgclk.eq(ClockSignal())
         if self.ti.dbg_domain != 'sync':
             dbgclk = ClockSignal(self.ti.dbg_domain)
             comb += dbgclk.eq(intclk)
-- 
2.30.2