From 693fc45eb8ccc3c9f84b898de3119a172e0776f5 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Tue, 21 Mar 2017 20:53:09 -0700 Subject: [PATCH] sim: declare cores as interrupt-controllers for clint --- riscv/sim.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/riscv/sim.cc b/riscv/sim.cc index a2b5cd1..bdf55e2 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -276,6 +276,8 @@ void sim_t::make_dtb() " riscv,isa = \"" << procs[i]->isa_string << "\";\n" " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n" " clock-frequency = <" << CPU_HZ << ">;\n" + " interrupt-controller;\n" + " #interrupt-cells = <1>;\n" " };\n"; } reg_t membs = DRAM_BASE; -- 2.30.2