From 697e55995626f24658ce443287cd1ba90c2f68eb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 29 Oct 2019 19:31:37 -0700 Subject: [PATCH] arch: Make and use endian specific versions of the mem helpers. Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini Maintainer: Gabe Black Tested-by: kokoro --- src/arch/alpha/isa/mem.isa | 10 +-- src/arch/arm/isa/templates/mem.isa | 29 ++++--- src/arch/arm/isa/templates/mem64.isa | 28 +++--- src/arch/arm/isa/templates/sve_mem.isa | 14 +-- src/arch/generic/memhelpers.hh | 109 +++++++++++++++++++++--- src/arch/mips/isa/formats/mem.isa | 14 +-- src/arch/power/isa/formats/mem.isa | 8 +- src/arch/riscv/isa/formats/amo.isa | 12 +-- src/arch/riscv/isa/formats/mem.isa | 8 +- src/arch/sparc/isa/formats/mem/swap.isa | 6 +- src/arch/sparc/isa/formats/mem/util.isa | 10 ++- 11 files changed, 168 insertions(+), 80 deletions(-) diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index 3cdab6f47..a8c534c89 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -158,7 +158,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -201,7 +201,7 @@ def template LoadCompleteAcc {{ %(fp_enable_check)s; %(op_decl)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -233,7 +233,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -267,7 +267,7 @@ def template StoreCondExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, &write_result); } @@ -300,7 +300,7 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa index aa63d4b57..404c265dc 100644 --- a/src/arch/arm/isa/templates/mem.isa +++ b/src/arch/arm/isa/templates/mem.isa @@ -86,8 +86,8 @@ def template SwapExecute {{ %(preacc_code)s; if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, - &memData); + fault = writeMemAtomicLE(xc, traceData, Mem, EA, + memAccessFlags, &memData); } if (fault == NoFault) { @@ -122,8 +122,8 @@ def template SwapInitiateAcc {{ %(preacc_code)s; if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, - &memData); + fault = writeMemTimingLE(xc, traceData, Mem, EA, + memAccessFlags, &memData); } } else { xc->setPredicate(false); @@ -145,7 +145,7 @@ def template SwapCompleteAcc {{ if (%(predicate_test)s) { // ARM instructions will not have a pkt if the predicate is false - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); uint64_t memData = Mem; %(postacc_code)s; @@ -173,7 +173,8 @@ def template LoadExecute {{ if (%(predicate_test)s) { if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE( + xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -240,7 +241,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -313,8 +314,8 @@ def template StoreExExecute {{ uint64_t writeResult; if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, - &writeResult); + fault = writeMemAtomicLE(xc, traceData, Mem, EA, + memAccessFlags, &writeResult); } if (fault == NoFault) { @@ -350,8 +351,8 @@ def template StoreExInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, - NULL); + fault = writeMemTimingLE(xc, traceData, Mem, EA, + memAccessFlags, NULL); } } else { xc->setPredicate(false); @@ -379,8 +380,8 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, - NULL); + fault = writeMemTimingLE(xc, traceData, Mem, EA, + memAccessFlags, NULL); } } else { xc->setPredicate(false); @@ -485,7 +486,7 @@ def template LoadCompleteAcc {{ if (%(predicate_test)s) { // ARM instructions will not have a pkt if the predicate is false - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa index 3d0302a73..f5a42019a 100644 --- a/src/arch/arm/isa/templates/mem64.isa +++ b/src/arch/arm/isa/templates/mem64.isa @@ -58,7 +58,7 @@ def template Load64Execute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -82,7 +82,7 @@ def template Load64FpExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); } if (fault == NoFault) { @@ -110,8 +110,8 @@ def template Store64Execute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, - memAccessFlags, NULL); + fault = writeMemAtomicLE(xc, traceData, Mem, EA, + memAccessFlags, NULL); } if (fault == NoFault) { @@ -138,8 +138,8 @@ def template Store64InitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, - NULL); + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, + NULL); } return fault; @@ -163,8 +163,8 @@ def template StoreEx64Execute {{ uint64_t writeResult = 0; if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, - &writeResult); + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, + &writeResult); } if (fault == NoFault) { @@ -195,8 +195,8 @@ def template StoreEx64InitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, - NULL); + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, + NULL); } return fault; @@ -232,7 +232,7 @@ def template Load64CompleteAcc {{ %(op_rd)s; // ARM instructions will not have a pkt if the predicate is false - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -749,8 +749,8 @@ def template AmoOpExecute {{ %(amo_code)s; assert(amo_op); - const Fault fault = amoMemAtomic(xc, traceData, Mem, EA, - memAccessFlags, amo_op); + const Fault fault = amoMemAtomicLE(xc, traceData, Mem, EA, + memAccessFlags, amo_op); if (fault == NoFault) { %(postacc_code)s; @@ -790,7 +790,7 @@ def template AmoOpCompleteAcc {{ %(op_rd)s; // ARM instructions will not have a pkt if the predicate is false - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); %(postacc_code)s; diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa index 3085eca6d..933a78494 100644 --- a/src/arch/arm/isa/templates/sve_mem.isa +++ b/src/arch/arm/isa/templates/sve_mem.isa @@ -317,7 +317,7 @@ def template SveLoadAndReplExecute {{ MemElemType memData; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, memData, + fault = readMemAtomicLE(xc, traceData, EA, memData, this->memAccessFlags); %(memacc_code)s; } @@ -369,7 +369,7 @@ def template SveLoadAndReplCompleteAcc {{ %(op_rd)s; MemElemType memData; - getMem(pkt, memData, traceData); + getMemLE(pkt, memData, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -553,7 +553,7 @@ def template SveGatherLoadMicroopExecute {{ int index = elemIndex; if (%(pred_check_code)s) { - fault = readMemAtomic(xc, traceData, EA, memData, + fault = readMemAtomicLE(xc, traceData, EA, memData, this->memAccessFlags); } @@ -638,7 +638,7 @@ def template SveGatherLoadMicroopCompleteAcc {{ MemElemType memData = 0; if (xc->readMemAccPredicate()) { - getMem(pkt, memData, traceData); + getMemLE(pkt, memData, traceData); } %(memacc_code)s; @@ -668,8 +668,8 @@ def template SveScatterStoreMicroopExecute {{ int index = elemIndex; if (%(pred_check_code)s) { - fault = writeMemAtomic(xc, traceData, memData, EA, - this->memAccessFlags, NULL); + fault = writeMemAtomicLE(xc, traceData, memData, EA, + this->memAccessFlags, NULL); } if (fault == NoFault) { @@ -698,7 +698,7 @@ def template SveScatterStoreMicroopInitiateAcc {{ int index = elemIndex; if (%(pred_check_code)s) { - fault = writeMemTiming(xc, traceData, memData, EA, + fault = writeMemTimingLE(xc, traceData, memData, EA, this->memAccessFlags, NULL); } else { xc->setPredicate(false); diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh index fa1af2694..62866bf0c 100644 --- a/src/arch/generic/memhelpers.hh +++ b/src/arch/generic/memhelpers.hh @@ -62,17 +62,31 @@ initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr, } /// Extract the data returned from a timing mode read. -template +template void getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) { - mem = pkt->get(TheISA::GuestByteOrder); + mem = pkt->get(Order); if (traceData) traceData->setData(mem); } +template +void +getMemLE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) +{ + getMem(pkt, mem, traceData); +} + +template +void +getMemBE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData) +{ + getMem(pkt, mem, traceData); +} + /// Read from memory in atomic mode. -template +template Fault readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, Request::Flags flags) @@ -80,50 +94,103 @@ readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, memset(&mem, 0, sizeof(mem)); Fault fault = xc->readMem(addr, (uint8_t *)&mem, sizeof(MemT), flags); if (fault == NoFault) { - mem = TheISA::gtoh(mem); + mem = gtoh(mem, Order); if (traceData) traceData->setData(mem); } return fault; } -/// Write to memory in timing mode. template Fault +readMemAtomicLE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, + Request::Flags flags) +{ + return readMemAtomic( + xc, traceData, addr, mem, flags); +} + +template +Fault +readMemAtomicBE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem, + Request::Flags flags) +{ + return readMemAtomic(xc, traceData, addr, mem, flags); +} + +/// Write to memory in timing mode. +template +Fault writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, Request::Flags flags, uint64_t *res) { if (traceData) { traceData->setData(mem); } - mem = TheISA::htog(mem); + mem = htog(mem, Order); return xc->writeMem((uint8_t *)&mem, sizeof(MemT), addr, flags, res); } -/// Write to memory in atomic mode. template Fault +writeMemTimingLE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, + Request::Flags flags, uint64_t *res) +{ + return writeMemTiming( + xc, traceData, mem, addr, flags, res); +} + +template +Fault +writeMemTimingBE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr, + Request::Flags flags, uint64_t *res) +{ + return writeMemTiming( + xc, traceData, mem, addr, flags, res); +} + +/// Write to memory in atomic mode. +template +Fault writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem, Addr addr, Request::Flags flags, uint64_t *res) { if (traceData) { traceData->setData(mem); } - MemT host_mem = TheISA::htog(mem); + MemT host_mem = htog(mem, Order); Fault fault = xc->writeMem((uint8_t *)&host_mem, sizeof(MemT), addr, flags, res); if (fault == NoFault && res != NULL) { if (flags & Request::MEM_SWAP || flags & Request::MEM_SWAP_COND) - *(MemT *)res = TheISA::gtoh(*(MemT *)res); + *(MemT *)res = gtoh(*(MemT *)res, Order); else - *res = TheISA::gtoh(*res); + *res = gtoh(*res, Order); } return fault; } -/// Do atomic read-modify-write (AMO) in atomic mode template Fault +writeMemAtomicLE(XC *xc, Trace::InstRecord *traceData, const MemT &mem, + Addr addr, Request::Flags flags, uint64_t *res) +{ + return writeMemAtomic( + xc, traceData, mem, addr, flags, res); +} + +template +Fault +writeMemAtomicBE(XC *xc, Trace::InstRecord *traceData, const MemT &mem, + Addr addr, Request::Flags flags, uint64_t *res) +{ + return writeMemAtomic( + xc, traceData, mem, addr, flags, res); +} + +/// Do atomic read-modify-write (AMO) in atomic mode +template +Fault amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, Request::Flags flags, AtomicOpFunctor *_amo_op) { @@ -137,13 +204,31 @@ amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, std::move(amo_op)); if (fault == NoFault) { - mem = TheISA::gtoh(mem); + mem = gtoh(mem, Order); if (traceData) traceData->setData(mem); } return fault; } +template +Fault +amoMemAtomicLE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, + Request::Flags flags, AtomicOpFunctor *_amo_op) +{ + return amoMemAtomic( + xc, traceData, mem, addr, flags, _amo_op); +} + +template +Fault +amoMemAtomicBE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr, + Request::Flags flags, AtomicOpFunctor *_amo_op) +{ + return amoMemAtomic( + xc, traceData, mem, addr, flags, _amo_op); +} + /// Do atomic read-modify-wrote (AMO) in timing mode template Fault diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa index e2204db6f..054690f2e 100644 --- a/src/arch/mips/isa/formats/mem.isa +++ b/src/arch/mips/isa/formats/mem.isa @@ -175,7 +175,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -230,7 +230,7 @@ def template LoadCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -261,7 +261,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -297,7 +297,7 @@ def template StoreFPExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -331,7 +331,7 @@ def template StoreCondExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, &write_result); } @@ -364,7 +364,7 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -523,7 +523,7 @@ def format StoreUnalignedMemory(memacc_code, ea_code = {{ EA = (Rs + disp) & ~3; uint32_t byte_offset = unaligned_addr & 3; if (GuestByteOrder == BigEndianByteOrder) byte_offset ^= 3; - fault = readMemAtomic(xc, traceData, EA, mem_word, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, mem_word, memAccessFlags); ''' memacc_code = decl_code + memacc_code + '\nMem = mem_word;\n' diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa index 47ffc916b..846d6b6b8 100644 --- a/src/arch/power/isa/formats/mem.isa +++ b/src/arch/power/isa/formats/mem.isa @@ -73,7 +73,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicBE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -119,7 +119,7 @@ def template LoadCompleteAcc {{ EA = pkt->req->getVaddr(); - getMem(pkt, Mem, traceData); + getMemBE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -150,7 +150,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicBE(xc, traceData, Mem, EA, memAccessFlags, NULL); } @@ -179,7 +179,7 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemTimingBE(xc, traceData, Mem, EA, memAccessFlags, NULL); } diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa index cc7346aa8..a115ccd93 100644 --- a/src/arch/riscv/isa/formats/amo.isa +++ b/src/arch/riscv/isa/formats/amo.isa @@ -227,7 +227,7 @@ def template LoadReservedExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -256,7 +256,7 @@ def template StoreCondExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, &result); // RISC-V has the opposite convention gem5 has for success flags, // so we invert the result here. @@ -290,7 +290,7 @@ def template AtomicMemOpRMWExecute {{ assert(amo_op); if (fault == NoFault) { - fault = amoMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = amoMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, amo_op); %(memacc_code)s; } @@ -346,7 +346,7 @@ def template StoreCondInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } @@ -394,7 +394,7 @@ def template LoadReservedCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -441,7 +441,7 @@ def template AtomicMemOpRMWCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa index a932d01cc..1e416d87e 100644 --- a/src/arch/riscv/isa/formats/mem.isa +++ b/src/arch/riscv/isa/formats/mem.isa @@ -106,7 +106,7 @@ def template LoadExecute {{ %(ea_code)s; if (fault == NoFault) { - fault = readMemAtomic(xc, traceData, EA, Mem, memAccessFlags); + fault = readMemAtomicLE(xc, traceData, EA, Mem, memAccessFlags); %(memacc_code)s; } @@ -148,7 +148,7 @@ def template LoadCompleteAcc {{ %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemLE(pkt, Mem, traceData); if (fault == NoFault) { %(memacc_code)s; @@ -179,7 +179,7 @@ def template StoreExecute {{ } if (fault == NoFault) { - fault = writeMemAtomic(xc, traceData, Mem, EA, memAccessFlags, + fault = writeMemAtomicLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } @@ -212,7 +212,7 @@ def template StoreInitiateAcc {{ } if (fault == NoFault) { - fault = writeMemTiming(xc, traceData, Mem, EA, + fault = writeMemTimingLE(xc, traceData, Mem, EA, memAccessFlags, nullptr); } diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa index fcabc33e4..f8c4e900d 100644 --- a/src/arch/sparc/isa/formats/mem/swap.isa +++ b/src/arch/sparc/isa/formats/mem/swap.isa @@ -50,7 +50,7 @@ def template SwapExecute {{ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = writeMemAtomic(xc, traceData, Mem, EA, + fault = writeMemAtomicBE(xc, traceData, Mem, EA, %(asi_val)s, &mem_data); } if (fault == NoFault) { @@ -87,7 +87,7 @@ def template SwapInitiateAcc {{ } if (fault == NoFault) { %(EA_trunc)s - fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, + fault = writeMemTimingBE(xc, traceData, Mem, EA, %(asi_val)s, &mem_data); } return fault; @@ -103,7 +103,7 @@ def template SwapCompleteAcc {{ Fault fault = NoFault; %(op_decl)s; - getMem(pkt, Mem, traceData); + getMemBE(pkt, Mem, traceData); uint64_t mem_data = Mem; if (fault == NoFault) { diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 8711cb812..5ee4143df 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -48,7 +48,7 @@ def template LoadExecute {{ %(fault_check)s; if (fault == NoFault) { %(EA_trunc)s - fault = readMemAtomic(xc, traceData, EA, Mem, %(asi_val)s); + fault = readMemAtomicBE(xc, traceData, EA, Mem, %(asi_val)s); } if (fault == NoFault) { %(code)s; @@ -89,7 +89,7 @@ def template LoadCompleteAcc {{ Fault fault = NoFault; %(op_decl)s; %(op_rd)s; - getMem(pkt, Mem, traceData); + getMemBE(pkt, Mem, traceData); %(code)s; if (fault == NoFault) { %(op_wb)s; @@ -119,7 +119,8 @@ def template StoreExecute {{ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = writeMemAtomic(xc, traceData, Mem, EA, %(asi_val)s, 0); + fault = writeMemAtomicBE( + xc, traceData, Mem, EA, %(asi_val)s, 0); } if (fault == NoFault) { // Write the resulting state to the execution context @@ -149,7 +150,8 @@ def template StoreInitiateAcc {{ } if (storeCond && fault == NoFault) { %(EA_trunc)s - fault = writeMemTiming(xc, traceData, Mem, EA, %(asi_val)s, 0); + fault = writeMemTimingBE( + xc, traceData, Mem, EA, %(asi_val)s, 0); } return fault; } -- 2.30.2