From 6981bbfabeeaf60111d737dd0d5a93496fd16758 Mon Sep 17 00:00:00 2001 From: Keith Whitwell Date: Sun, 1 Nov 2009 15:59:21 +0000 Subject: [PATCH] i965g: more files compiling --- src/gallium/drivers/i965/Makefile | 3 +- src/gallium/drivers/i965/brw_context.h | 8 +- src/gallium/drivers/i965/brw_pipe_blend.c | 2 + src/gallium/drivers/i965/brw_pipe_rast.c | 199 ++++++++++++------ .../drivers/i965/brw_screen_tex_layout.c | 29 +++ src/gallium/drivers/i965/brw_screen_texture.c | 157 ++++++++------ src/gallium/drivers/i965/brw_winsys.h | 8 +- .../drivers/i965/brw_wm_sampler_state.c | 10 +- 8 files changed, 269 insertions(+), 147 deletions(-) diff --git a/src/gallium/drivers/i965/Makefile b/src/gallium/drivers/i965/Makefile index d88f34cb7e2..48950544c9a 100644 --- a/src/gallium/drivers/i965/Makefile +++ b/src/gallium/drivers/i965/Makefile @@ -31,6 +31,7 @@ C_SOURCES = \ brw_pipe_query.c \ brw_pipe_shader.c \ brw_pipe_flush.c \ + brw_pipe_rast.c \ brw_sf.c \ brw_sf_emit.c \ brw_sf_state.c \ @@ -57,8 +58,8 @@ C_SOURCES = \ brw_wm_state.c \ brw_wm_surface_state.c \ brw_screen_tex_layout.c \ - brw_screen_surface.c \ brw_screen_texture.c \ + brw_screen_surface.c \ brw_batchbuffer.c include ../../Makefile.template diff --git a/src/gallium/drivers/i965/brw_context.h b/src/gallium/drivers/i965/brw_context.h index 3e9315c41f0..b94c5114995 100644 --- a/src/gallium/drivers/i965/brw_context.h +++ b/src/gallium/drivers/i965/brw_context.h @@ -102,7 +102,7 @@ * * CS - Clipper. Mesa's clipping algorithms are imported to run on * this unit. The fixed function part performs cliptesting against - * the 6 fixed clipplanes and makes descisions on whether or not the + * the 6 fixed clipplanes and makes decisions on whether or not the * incoming primitive needs to be passed to a thread for clipping. * User clip planes are handled via cooperation with the VS thread. * @@ -123,8 +123,6 @@ struct brw_context; struct brw_depth_stencil_state { - //struct pipe_depth_stencil_alpha_state templ; /* for draw module */ - /* Precalculated hardware state: */ struct brw_cc0 cc0; @@ -138,8 +136,6 @@ struct brw_depth_stencil_state { struct brw_blend_state { - //struct pipe_depth_stencil_alpha_state templ; /* for draw module */ - /* Precalculated hardware state: */ struct brw_cc2 cc2; @@ -181,7 +177,7 @@ struct brw_fragment_shader { struct brw_sampler { - struct pipe_sampler_state templ; + float border_color[4]; struct brw_ss0 ss0; struct brw_ss1 ss1; struct brw_ss3 ss3; diff --git a/src/gallium/drivers/i965/brw_pipe_blend.c b/src/gallium/drivers/i965/brw_pipe_blend.c index cc9ee2e8dbc..f6da9254ef1 100644 --- a/src/gallium/drivers/i965/brw_pipe_blend.c +++ b/src/gallium/drivers/i965/brw_pipe_blend.c @@ -111,6 +111,8 @@ static void *brw_create_blend_state( struct pipe_context *pipe, const struct pipe_blend_state *templ ) { struct brw_blend_state *blend = CALLOC_STRUCT(brw_blend_state); + if (blend == NULL) + return NULL; if (templ->logicop_enable) { blend->cc2.logicop_enable = 1; diff --git a/src/gallium/drivers/i965/brw_pipe_rast.c b/src/gallium/drivers/i965/brw_pipe_rast.c index 51159bf1471..27c568de0a8 100644 --- a/src/gallium/drivers/i965/brw_pipe_rast.c +++ b/src/gallium/drivers/i965/brw_pipe_rast.c @@ -1,84 +1,159 @@ -static void -calculate_clip_key_rast() -{ - if (BRW_IS_IGDNG(brw)) - key.clip_mode = BRW_CLIPMODE_KERNEL_CLIP; - else - key.clip_mode = BRW_CLIPMODE_NORMAL; +#include "util/u_memory.h" +#include "pipe/p_defines.h" +#include "brw_context.h" +#include "brw_defines.h" +#include "brw_pipe_rast.h" +#include "brw_wm.h" - key.do_flat_shading = brw->rast->templ.flatshade; - if (key.primitive == PIPE_PRIM_TRIANGLES) { - if (brw->rast->templ.cull_mode = PIPE_WINDING_BOTH) - key.clip_mode = BRW_CLIPMODE_REJECT_ALL; - else { - key.fill_ccw = CLIP_CULL; - key.fill_cw = CLIP_CULL; - - if (!(brw->rast->templ.cull_mode & PIPE_WINDING_CCW)) { - key.fill_ccw = translate_fill(brw->rast.fill_ccw); - } - - if (!(brw->rast->templ.cull_mode & PIPE_WINDING_CW)) { - key.fill_cw = translate_fill(brw->rast.fill_cw); - } - - if (key.fill_cw != CLIP_FILL || - key.fill_ccw != CLIP_FILL) { - key.do_unfilled = 1; - key.clip_mode = BRW_CLIPMODE_CLIP_NON_REJECTED; - } - - key.offset_ccw = brw->rast.templ.offset_ccw; - key.offset_cw = brw->rast.templ.offset_cw; - - if (brw->rast.templ.light_twoside && - key.fill_cw != CLIP_CULL) - key.copy_bfc_cw = 1; - - if (brw->rast.templ.light_twoside && - key.fill_ccw != CLIP_CULL) - key.copy_bfc_ccw = 1; - } - } +static unsigned translate_fill( unsigned fill ) +{ + switch (fill) { + case PIPE_POLYGON_MODE_FILL: + return CLIP_FILL; + case PIPE_POLYGON_MODE_LINE: + return CLIP_LINE; + case PIPE_POLYGON_MODE_POINT: + return CLIP_POINT; + default: + assert(0); + return CLIP_FILL; } } +/* Calculates the key for triangle-mode clipping. Non-triangle + * clipping keys use much less information and are computed on the + * fly. + */ static void -calculate_line_stipple_rast() +calculate_clip_key_rast( const struct brw_context *brw, + const struct pipe_rasterizer_state *templ, + const struct brw_rasterizer_state *rast, + struct brw_clip_prog_key *key) { - GLfloat tmp; - GLint tmpi; + memset(key, 0, sizeof *key); - memset(&bls, 0, sizeof(bls)); - bls.header.opcode = CMD_LINE_STIPPLE_PATTERN; - bls.header.length = sizeof(bls)/4 - 2; - bls.bits0.pattern = brw->curr.rast.line_stipple_pattern; - bls.bits1.repeat_count = brw->curr.rast.line_stipple_factor + 1; + if (brw->chipset.is_igdng) + key->clip_mode = BRW_CLIPMODE_KERNEL_CLIP; + else + key->clip_mode = BRW_CLIPMODE_NORMAL; - tmp = 1.0 / (GLfloat) bls.bits1.repeat_count; - tmpi = tmp * (1<<13); + key->do_flat_shading = templ->flatshade; - bls.bits1.inverse_repeat_count = tmpi; + if (templ->cull_mode == PIPE_WINDING_BOTH) { + key->clip_mode = BRW_CLIPMODE_REJECT_ALL; + return; + } -} + key->fill_ccw = CLIP_CULL; + key->fill_cw = CLIP_CULL; + if (!(templ->cull_mode & PIPE_WINDING_CCW)) { + key->fill_ccw = translate_fill(templ->fill_ccw); + } + + if (!(templ->cull_mode & PIPE_WINDING_CW)) { + key->fill_cw = translate_fill(templ->fill_cw); + } + + if (key->fill_cw != CLIP_FILL || + key->fill_ccw != CLIP_FILL) { + key->do_unfilled = 1; + key->clip_mode = BRW_CLIPMODE_CLIP_NON_REJECTED; + } + + key->offset_ccw = templ->offset_ccw; + key->offset_cw = templ->offset_cw; + + if (templ->light_twoside && key->fill_cw != CLIP_CULL) + key->copy_bfc_cw = 1; + + if (templ->light_twoside && key->fill_ccw != CLIP_CULL) + key->copy_bfc_ccw = 1; +} static void -calculate_wm_lookup() +calculate_line_stipple_rast( const struct pipe_rasterizer_state *templ, + struct brw_line_stipple *bls ) { - if (rast->fill_cw == PIPE_POLYGON_MODE_LINE && - rast->fill_ccw == PIPE_POLYGON_MODE_LINE) { - line_aa = AA_ALWAYS; - } - else if (rast->fill_cw == PIPE_POLYGON_MODE_LINE || - rast->fill_ccw == PIPE_POLYGON_MODE_LINE) { - line_aa = AA_SOMETIMES; + GLfloat tmp = 1.0f / (templ->line_stipple_factor + 1); + GLint tmpi = tmp * (1<<13); + + bls->header.opcode = CMD_LINE_STIPPLE_PATTERN; + bls->header.length = sizeof(*bls)/4 - 2; + bls->bits0.pattern = templ->line_stipple_pattern; + bls->bits1.repeat_count = templ->line_stipple_factor + 1; + bls->bits1.inverse_repeat_count = tmpi; +} + +static void *brw_create_rasterizer_state( struct pipe_context *pipe, + const struct pipe_rasterizer_state *templ ) +{ + struct brw_context *brw = brw_context(pipe); + struct brw_rasterizer_state *rast; + + rast = CALLOC_STRUCT(brw_rasterizer_state); + if (rast == NULL) + return NULL; + + rast->templ = *templ; + + calculate_clip_key_rast( brw, templ, rast, &rast->clip_key ); + + if (templ->line_stipple_enable) + calculate_line_stipple_rast( templ, &rast->bls ); + + /* Caclculate lookup value for WM IZ table. + */ + if (templ->line_smooth) { + if (templ->fill_cw == PIPE_POLYGON_MODE_LINE && + templ->fill_ccw == PIPE_POLYGON_MODE_LINE) { + rast->unfilled_aa_line = AA_ALWAYS; + } + else if (templ->fill_cw == PIPE_POLYGON_MODE_LINE || + templ->fill_ccw == PIPE_POLYGON_MODE_LINE) { + rast->unfilled_aa_line = AA_SOMETIMES; + } + else { + rast->unfilled_aa_line = AA_NEVER; + } } else { - line_aa = AA_NEVER; + rast->unfilled_aa_line = AA_NEVER; } + + return (void *)rast; +} + + +static void brw_bind_rasterizer_state(struct pipe_context *pipe, + void *cso) +{ + struct brw_context *brw = brw_context(pipe); + brw->curr.rast = (const struct brw_rasterizer_state *)cso; + brw->state.dirty.mesa |= PIPE_NEW_RAST; +} + +static void brw_delete_rasterizer_state(struct pipe_context *pipe, + void *cso) +{ + struct brw_context *brw = brw_context(pipe); + assert((const void *)cso != (const void *)brw->curr.rast); + FREE(cso); +} + + + +void brw_pipe_rast_init( struct brw_context *brw ) +{ + brw->base.create_rasterizer_state = brw_create_rasterizer_state; + brw->base.bind_rasterizer_state = brw_bind_rasterizer_state; + brw->base.delete_rasterizer_state = brw_delete_rasterizer_state; +} + +void brw_pipe_rast_cleanup( struct brw_context *brw ) +{ } diff --git a/src/gallium/drivers/i965/brw_screen_tex_layout.c b/src/gallium/drivers/i965/brw_screen_tex_layout.c index 8377d30564b..bcdf8d8074f 100644 --- a/src/gallium/drivers/i965/brw_screen_tex_layout.c +++ b/src/gallium/drivers/i965/brw_screen_tex_layout.c @@ -1,3 +1,29 @@ +/* + Copyright (C) Intel Corp. 2006. All Rights Reserved. + Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to + develop this 3D driver. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice (including the + next paragraph) shall be included in all copies or substantial + portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE + LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION + OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION + WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + **********************************************************************/ #include "pipe/p_format.h" @@ -7,6 +33,9 @@ #include "brw_screen.h" #include "brw_debug.h" +/* Code to layout images in a mipmap tree for i965. + */ + static int brw_tex_pitch_align (struct brw_texture *tex, int pitch) diff --git a/src/gallium/drivers/i965/brw_screen_texture.c b/src/gallium/drivers/i965/brw_screen_texture.c index d527f22a8d3..989013953bc 100644 --- a/src/gallium/drivers/i965/brw_screen_texture.c +++ b/src/gallium/drivers/i965/brw_screen_texture.c @@ -29,12 +29,12 @@ * Keith Whitwell */ -/* Code to layout images in a mipmap tree for i965. - */ +#include "util/u_memory.h" -#include "brw_tex_layout.h" - -#define FILE_DEBUG_FLAG DEBUG_MIPTREE +#include "brw_screen.h" +#include "brw_defines.h" +#include "brw_structs.h" +#include "brw_winsys.h" @@ -176,94 +176,113 @@ static GLuint translate_tex_format( enum pipe_format pf ) } } -static void -brw_set_surface_tiling(struct brw_surface_state *surf, uint32_t tiling) -{ - switch (tiling) { - case BRW_TILING_NONE: - surf->ss3.tiled_surface = 0; - surf->ss3.tile_walk = 0; - break; - case BRW_TILING_X: - surf->ss3.tiled_surface = 1; - surf->ss3.tile_walk = BRW_TILEWALK_XMAJOR; - break; - case BRW_TILING_Y: - surf->ss3.tiled_surface = 1; - surf->ss3.tile_walk = BRW_TILEWALK_YMAJOR; - break; - } -} -static void brw_create_texture( struct pipe_screen *screen, - const pipe_texture *templ ) +static struct pipe_texture *brw_create_texture( struct pipe_screen *screen, + const struct pipe_texture *templ ) { + struct brw_screen *bscreen = brw_screen(screen); + struct brw_texture *tex; + + tex = CALLOC_STRUCT(brw_texture); + if (tex == NULL) + return NULL; tex->compressed = pf_is_compressed(tex->base.format); - if (intel->use_texture_tiling && compress_byte == 0 && - intel->intelScreen->kernel_exec_fencing) { - if (IS_965(intel->intelScreen->deviceID) && - (base_format == GL_DEPTH_COMPONENT || - base_format == GL_DEPTH_STENCIL_EXT)) - tiling = I915_TILING_Y; + /* XXX: No tiling with compressed textures?? + */ + if (tex->compressed == 0 + /* && bscreen->use_texture_tiling */ + /* && bscreen->kernel_exec_fencing */) + { + if (bscreen->chipset.is_965 && + pf_is_depth_or_stencil(templ->format)) + tex->tiling = BRW_TILING_Y; else - tiling = I915_TILING_X; - } else - tiling = I915_TILING_NONE; + tex->tiling = BRW_TILING_X; + } + else { + tex->tiling = BRW_TILING_NONE; + } + memcpy(&tex->base, templ, sizeof *templ); - key.format = tex->base.format; - key.pitch = tex->pitch; - key.depth = tex->base.depth[0]; - key.bo = tex->buffer; - key.offset = 0; + if (!brw_texture_layout( bscreen, tex )) + goto fail; - key.target = tex->brw_target; /* translated to BRW enum */ - //key.depthmode = 0; /* XXX: add this to gallium? or handle in the state tracker? */ - key.last_level = tex->base.last_level; - key.width = tex->base.depth[0]; - key.height = tex->base.height[0]; - key.cpp = tex->cpp; - key.tiling = tex->tiling; + tex->ss.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; + tex->ss.ss0.surface_type = translate_tex_target(tex->base.target); + tex->ss.ss0.surface_format = translate_tex_format(tex->base.format); + /* This is ok for all textures with channel width 8bit or less: + */ +/* tex->ss.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ + tex->ss.ss1.base_addr = tex->bo->offset; /* reloc */ + tex->ss.ss2.mip_count = tex->base.last_level; + tex->ss.ss2.width = tex->base.width[0] - 1; + tex->ss.ss2.height = tex->base.height[0] - 1; + switch (tex->tiling) { + case BRW_TILING_NONE: + tex->ss.ss3.tiled_surface = 0; + tex->ss.ss3.tile_walk = 0; + break; + case BRW_TILING_X: + tex->ss.ss3.tiled_surface = 1; + tex->ss.ss3.tile_walk = BRW_TILEWALK_XMAJOR; + break; + case BRW_TILING_Y: + tex->ss.ss3.tiled_surface = 1; + tex->ss.ss3.tile_walk = BRW_TILEWALK_YMAJOR; + break; + } - surf.ss0.mipmap_layout_mode = BRW_SURFACE_MIPMAPLAYOUT_BELOW; - surf.ss0.surface_type = translate_tex_target(key->target); - surf.ss0.surface_format = translate_tex_format(key->format /* , key->depthmode */ ); + tex->ss.ss3.pitch = (tex->pitch * tex->cpp) - 1; + tex->ss.ss3.depth = tex->base.depth[0] - 1; - /* This is ok for all textures with channel width 8bit or less: - */ -/* surf.ss0.data_return_format = BRW_SURFACERETURNFORMAT_S1; */ - assert(key->bo); - surf.ss1.base_addr = key->bo->offset; /* reloc */ - surf.ss2.mip_count = key->last_level; - surf.ss2.width = key->width - 1; - surf.ss2.height = key->height - 1; - brw_set_surface_tiling(&surf, key->tiling); - surf.ss3.pitch = (key->pitch * key->cpp) - 1; - surf.ss3.depth = key->depth - 1; - - surf.ss4.min_lod = 0; + tex->ss.ss4.min_lod = 0; - if (key->target == PIPE_TEXTURE_CUBE) { - surf.ss0.cube_pos_x = 1; - surf.ss0.cube_pos_y = 1; - surf.ss0.cube_pos_z = 1; - surf.ss0.cube_neg_x = 1; - surf.ss0.cube_neg_y = 1; - surf.ss0.cube_neg_z = 1; + if (tex->base.target == PIPE_TEXTURE_CUBE) { + tex->ss.ss0.cube_pos_x = 1; + tex->ss.ss0.cube_pos_y = 1; + tex->ss.ss0.cube_pos_z = 1; + tex->ss.ss0.cube_neg_x = 1; + tex->ss.ss0.cube_neg_y = 1; + tex->ss.ss0.cube_neg_z = 1; } + return &tex->base; + +fail: + bscreen->sws->bo_unreference(tex->bo); + FREE(tex); + return NULL; } +static struct pipe_texture *brw_texture_blanket(struct pipe_screen *screen, + const struct pipe_texture *templ, + const unsigned *stride, + struct pipe_buffer *buffer) +{ + return NULL; +} + +static void brw_texture_destroy(struct pipe_texture *pt) +{ + //bscreen->sws->bo_unreference(tex->bo); + FREE(pt); +} + + + + + diff --git a/src/gallium/drivers/i965/brw_winsys.h b/src/gallium/drivers/i965/brw_winsys.h index 33032276bc1..66a94b4b00f 100644 --- a/src/gallium/drivers/i965/brw_winsys.h +++ b/src/gallium/drivers/i965/brw_winsys.h @@ -243,10 +243,10 @@ boolean brw_get_texture_buffer_brw(struct pipe_texture *texture, * * TODO UGLY */ -struct pipe_texture * brw_texture_blanket(struct pipe_screen *screen, - struct pipe_texture *tmplt, - unsigned pitch, - struct brw_winsys_buffer *buffer); +struct pipe_texture * brw_texture_blanket_ws(struct pipe_screen *screen, + const struct pipe_texture *tmplt, + const unsigned *stride, + struct brw_winsys_buffer *buffer); diff --git a/src/gallium/drivers/i965/brw_wm_sampler_state.c b/src/gallium/drivers/i965/brw_wm_sampler_state.c index 55698a58bbc..ddd88d6e22e 100644 --- a/src/gallium/drivers/i965/brw_wm_sampler_state.c +++ b/src/gallium/drivers/i965/brw_wm_sampler_state.c @@ -126,10 +126,10 @@ brw_wm_sampler_update_default_colors(struct brw_context *brw) if (pf_is_depth_or_stencil(tex->base.format)) { float bordercolor[4] = { - sampler->templ.border_color[0], - sampler->templ.border_color[0], - sampler->templ.border_color[0], - sampler->templ.border_color[0] + sampler->border_color[0], + sampler->border_color[0], + sampler->border_color[0], + sampler->border_color[0] }; /* GL specs that border color for depth textures is taken from the * R channel, while the hardware uses A. Spam R into all the @@ -137,7 +137,7 @@ brw_wm_sampler_update_default_colors(struct brw_context *brw) */ brw->wm.sdc_bo[i] = upload_default_color(brw, bordercolor); } else { - brw->wm.sdc_bo[i] = upload_default_color(brw, sampler->templ.border_color); + brw->wm.sdc_bo[i] = upload_default_color(brw, sampler->border_color); } } } -- 2.30.2