From 6991f59619cefd42260ace8133d1bd2eda3ea4ba Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 22 Sep 2020 12:49:49 +0100 Subject: [PATCH] add sys_rst to Clock Reset Generator --- src/soc/litex/florent/ls180soc.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py index ef7d4451..660760e6 100755 --- a/src/soc/litex/florent/ls180soc.py +++ b/src/soc/litex/florent/ls180soc.py @@ -129,7 +129,8 @@ class LibreSoCSim(SoCCore): self.bus.add_slave(name='ics', slave=ics_wb, region=ics_region) # CRG ----------------------------------------------------------------- - self.submodules.crg = CRG(platform.request("sys_clk")) + self.submodules.crg = CRG(platform.request("sys_clk"), + platform.request("sys_rst")) #ram_init = [] -- 2.30.2