From 699cb33c8802d5807e9801a35ca0368ce7d6840c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 13 Dec 2021 12:26:35 +0000 Subject: [PATCH] change PortInterface naming to msr not msr_pr in set_wr_addr and set_rd_addr. the name-change does not affect any code at the moment --- src/soc/experiment/pimem.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py index 7077fbde..72e0834f 100644 --- a/src/soc/experiment/pimem.py +++ b/src/soc/experiment/pimem.py @@ -183,8 +183,8 @@ class PortInterfaceBase(Elaboratable): def connect_port(self, inport): return self.pi.connect_port(inport) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): pass - def set_rd_addr(self, m, addr, mask, misalign, msr_pr): pass + def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): pass + def set_rd_addr(self, m, addr, mask, misalign, msr): pass def set_wr_data(self, m, data, wen): pass def get_rd_data(self, m): pass @@ -364,11 +364,11 @@ class TestMemoryPortInterface(PortInterfaceBase): # hard-code memory addressing width to 6 bits self.mem = TestMemory(regwid, 5, granularity=regwid//8, init=False) - def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz): + def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz): lsbaddr, msbaddr = self.splitaddr(addr) m.d.comb += self.mem.wrport.addr.eq(msbaddr) - def set_rd_addr(self, m, addr, mask, misalign, msr_pr): + def set_rd_addr(self, m, addr, mask, misalign, msr): lsbaddr, msbaddr = self.splitaddr(addr) m.d.comb += self.mem.rdport.addr.eq(msbaddr) -- 2.30.2