From 69b1dda5d9b184ff39d4e9c134f66a5bfe5bcef6 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Fri, 14 Apr 2017 07:56:32 -0700
Subject: [PATCH] debug: working with newprogram branch

---
 debug/targets.py                           |  4 ++--
 debug/targets/freedom-e300-sim/openocd.cfg |  3 +--
 debug/targets/freedom-u500-sim/openocd.cfg |  4 +++-
 debug/testlib.py                           | 10 +++++-----
 4 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/debug/targets.py b/debug/targets.py
index 52b623c..043652c 100644
--- a/debug/targets.py
+++ b/debug/targets.py
@@ -99,7 +99,7 @@ class HiFive1Target(FreedomE300Target):
 class FreedomE300SimTarget(Target):
     name = "freedom-e300-sim"
     xlen = 32
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
@@ -119,7 +119,7 @@ class FreedomU500Target(Target):
 class FreedomU500SimTarget(Target):
     name = "freedom-u500-sim"
     xlen = 64
-    timeout_sec = 240
+    timeout_sec = 6000
     ram = 0x80000000
     ram_size = 256 * 1024 * 1024
     instruction_hardware_breakpoint_count = 2
diff --git a/debug/targets/freedom-e300-sim/openocd.cfg b/debug/targets/freedom-e300-sim/openocd.cfg
index 0b80885..f3d9cb4 100644
--- a/debug/targets/freedom-e300-sim/openocd.cfg
+++ b/debug/targets/freedom-e300-sim/openocd.cfg
@@ -7,8 +7,7 @@ set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 init
-
 halt
diff --git a/debug/targets/freedom-u500-sim/openocd.cfg b/debug/targets/freedom-u500-sim/openocd.cfg
index 0b80885..9239c83 100644
--- a/debug/targets/freedom-u500-sim/openocd.cfg
+++ b/debug/targets/freedom-u500-sim/openocd.cfg
@@ -2,13 +2,15 @@ adapter_khz     10000
 
 source [find interface/jtag_vpi.cfg]
 jtag_vpi_set_port $::env(JTAG_VPI_PORT)
+#jtag_vpi_set_port 44005
 
 set _CHIPNAME riscv
 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 
 init
 
 halt
+echo "OK GO NOW"
diff --git a/debug/testlib.py b/debug/testlib.py
index a762174..5a5d6e3 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -166,7 +166,7 @@ class Openocd(object):
         messaged = False
         while True:
             log = open(Openocd.logname).read()
-            if "Examined RISCV core" in log:
+            if "OK GO NOW" in log:
                 break
             if not self.process.poll() is None:
                 raise Exception(
@@ -203,7 +203,7 @@ class Openocd(object):
             elif matches:
                 [match] = matches
                 return int(match.group('port'))
-            time.sleep(0.1)
+            time.sleep(1)
         raise Exception("Timed out waiting for gdb server to obtain port.")
 
     def __del__(self):
@@ -261,7 +261,7 @@ class Gdb(object):
         """Wait for prompt."""
         self.child.expect(r"\(gdb\)")
 
-    def command(self, command, timeout=-1):
+    def command(self, command, timeout=6000):
         self.child.sendline(command)
         self.child.expect("\n", timeout=timeout)
         self.child.expect(r"\(gdb\)", timeout=timeout)
@@ -278,7 +278,7 @@ class Gdb(object):
 
     def interrupt(self):
         self.child.send("\003")
-        self.child.expect(r"\(gdb\)", timeout=60)
+        self.child.expect(r"\(gdb\)", timeout=6000)
         return self.child.before.strip()
 
     def x(self, address, size='w'):
@@ -311,7 +311,7 @@ class Gdb(object):
         return output
 
     def load(self):
-        output = self.command("load", timeout=60)
+        output = self.command("load", timeout=6000)
         assert "failed" not in  output
         assert "Transfer rate" in output
 
-- 
2.30.2