From 69c33e42260cfd7a81f9f0ac096690628cd5a47f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 4 May 2021 18:09:36 +0100 Subject: [PATCH] adding fast3 SPR to Trap pipeline and unit test --- src/soc/fu/trap/main_stage.py | 3 ++- src/soc/fu/trap/pipe_data.py | 6 ++++-- src/soc/fu/trap/test/test_pipe_caller.py | 11 ++++++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py index afc2e677..c720a184 100644 --- a/src/soc/fu/trap/main_stage.py +++ b/src/soc/fu/trap/main_stage.py @@ -64,7 +64,8 @@ class TrapMainStage(PipeModBase): comb = m.d.comb op = self.i.ctx.op msr_i = op.msr - nia_o, srr0_o, srr1_o = self.o.nia, self.o.srr0, self.o.srr1 + nia_o = self.o.nia + svsrr0_o, srr0_o, srr1_o = self.o.svsrr0, self.o.srr0, self.o.srr1 # trap address comb += nia_o.data.eq(trap_addr) diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py index 67b32b67..3ab8451d 100644 --- a/src/soc/fu/trap/pipe_data.py +++ b/src/soc/fu/trap/pipe_data.py @@ -7,13 +7,14 @@ class TrapInputData(FUBaseData): ('INT', 'rb', '0:63'), # RB/immediate ('FAST', 'fast1', '0:63'), # SRR0 ('FAST', 'fast2', '0:63'), # SRR1 + ('FAST', 'fast3', '0:63'), # SVSRR0 # note here that neither MSR nor CIA are read as regs: they are # passed in as incoming "State", via the CompTrapOpSubset ] def __init__(self, pspec): super().__init__(pspec, False) # convenience - self.srr0, self.srr1 = self.fast1, self.fast2 + self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3 self.a, self.b = self.ra, self.rb @@ -21,12 +22,13 @@ class TrapOutputData(FUBaseData): regspec = [('INT', 'o', '0:63'), # RA ('FAST', 'fast1', '0:63'), # SRR0 SPR ('FAST', 'fast2', '0:63'), # SRR1 SPR + ('FAST', 'fast3', '0:63'), # SRR2 SPR ('STATE', 'nia', '0:63'), # NIA (Next PC) ('STATE', 'msr', '0:63')] # MSR def __init__(self, pspec): super().__init__(pspec, True) # convenience - self.srr0, self.srr1 = self.fast1, self.fast2 + self.srr0, self.srr1, self.svsrr0 = self.fast1, self.fast2, self.fast3 diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 35d6b0ae..26b12ff6 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -35,8 +35,9 @@ def get_cu_inputs(dec2, sim): yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB - yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1 - yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR2 + yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR0 + yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR1 + yield from ALUHelpers.get_sim_fast_spr3(res, sim, dec2) # SVSRR0 ALUHelpers.get_sim_cia(res, sim, dec2) # PC ALUHelpers.get_sim_msr(res, sim, dec2) # MSR @@ -53,8 +54,9 @@ def set_alu_inputs(alu, dec2, sim): inp = yield from get_cu_inputs(dec2, sim) yield from ALUHelpers.set_int_ra(alu, dec2, inp) yield from ALUHelpers.set_int_rb(alu, dec2, inp) - yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR1 + yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR0 yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1 + yield from ALUHelpers.set_fast_spr3(alu, dec2, inp) # SVSRR0 # yield from ALUHelpers.set_cia(alu, dec2, inp) # yield from ALUHelpers.set_msr(alu, dec2, inp) @@ -170,6 +172,7 @@ class TestRunner(unittest.TestCase): yield from ALUHelpers.get_int_o(res, alu, dec2) yield from ALUHelpers.get_fast_spr1(res, alu, dec2) yield from ALUHelpers.get_fast_spr2(res, alu, dec2) + yield from ALUHelpers.get_fast_spr3(res, alu, dec2) yield from ALUHelpers.get_nia(res, alu, dec2) yield from ALUHelpers.get_msr(res, alu, dec2) @@ -178,6 +181,7 @@ class TestRunner(unittest.TestCase): yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2) yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2) yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2) + yield from ALUHelpers.get_wr_fast_spr3(sim_o, sim, dec2) ALUHelpers.get_sim_nia(sim_o, sim, dec2) ALUHelpers.get_sim_msr(sim_o, sim, dec2) @@ -186,6 +190,7 @@ class TestRunner(unittest.TestCase): ALUHelpers.check_int_o(self, res, sim_o, code) ALUHelpers.check_fast_spr1(self, res, sim_o, code) ALUHelpers.check_fast_spr2(self, res, sim_o, code) + ALUHelpers.check_fast_spr3(self, res, sim_o, code) ALUHelpers.check_nia(self, res, sim_o, code) ALUHelpers.check_msr(self, res, sim_o, code) -- 2.30.2