From 69c5fdcf6eaee5e20073aa76152ef7b402619998 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 20 Dec 2018 16:34:31 +0000 Subject: [PATCH] [AArch64][SVE] Add ABS support For some reason we missed ABS out of the list of supported integer operations when adding the SVE port initially. 2018-12-20 Richard Sandiford gcc/ * config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs. (SVE_FP_UNARY): Sort. gcc/testsuite/ * gcc.target/aarch64/pr64946.c: Force nosve. * gcc.target/aarch64/ssadv16qi.c: Likewise. * gcc.target/aarch64/usadv16qi.c: Likewise. * gcc.target/aarch64/vect-abs-compile.c: Likewise. * gcc.target/aarch64/sve/abs_1.c: New test. From-SVN: r267304 --- gcc/ChangeLog | 5 +++++ gcc/config/aarch64/iterators.md | 5 +++-- gcc/testsuite/ChangeLog | 8 +++++++ gcc/testsuite/gcc.target/aarch64/pr64946.c | 3 ++- gcc/testsuite/gcc.target/aarch64/ssadv16qi.c | 2 ++ gcc/testsuite/gcc.target/aarch64/sve/abs_1.c | 21 +++++++++++++++++++ gcc/testsuite/gcc.target/aarch64/usadv16qi.c | 2 ++ .../gcc.target/aarch64/vect-abs-compile.c | 3 ++- 8 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/abs_1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7d9c5c60325..5fa350f850b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-12-20 Richard Sandiford + + * config/aarch64/iterators.md (SVE_INT_UNARY, fp_int_op): Add abs. + (SVE_FP_UNARY): Sort. + 2018-12-20 Richard Sandiford * config/aarch64/aarch64-sve.md (*cond__4): Use diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index ae75666167d..a16b74c8c4a 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1209,10 +1209,10 @@ (define_code_iterator FAC_COMPARISONS [lt le ge gt]) ;; SVE integer unary operations. -(define_code_iterator SVE_INT_UNARY [neg not popcount]) +(define_code_iterator SVE_INT_UNARY [abs neg not popcount]) ;; SVE floating-point unary operations. -(define_code_iterator SVE_FP_UNARY [neg abs sqrt]) +(define_code_iterator SVE_FP_UNARY [abs neg sqrt]) ;; SVE integer binary operations. (define_code_iterator SVE_INT_BINARY [plus minus mult smax umax smin umin @@ -1401,6 +1401,7 @@ (mult "mul") (div "sdiv") (udiv "udiv") + (abs "abs") (neg "neg") (smin "smin") (smax "smax") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index da6182cd269..2cfdd7bb204 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2018-12-20 Richard Sandiford + + * gcc.target/aarch64/pr64946.c: Force nosve. + * gcc.target/aarch64/ssadv16qi.c: Likewise. + * gcc.target/aarch64/usadv16qi.c: Likewise. + * gcc.target/aarch64/vect-abs-compile.c: Likewise. + * gcc.target/aarch64/sve/abs_1.c: New test. + 2018-12-20 Richard Sandiford * gcc.target/aarch64/sve/fmla_2.c: New test. diff --git a/gcc/testsuite/gcc.target/aarch64/pr64946.c b/gcc/testsuite/gcc.target/aarch64/pr64946.c index 736656fcc96..ae79c0ccc26 100644 --- a/gcc/testsuite/gcc.target/aarch64/pr64946.c +++ b/gcc/testsuite/gcc.target/aarch64/pr64946.c @@ -1,7 +1,8 @@ - /* { dg-do compile } */ /* { dg-options "-O3" } */ +#pragma GCC target "+nosve" + signed char a[100],b[100]; void absolute_s8 (void) { diff --git a/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c b/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c index bab75992986..40b28843616 100644 --- a/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c +++ b/gcc/testsuite/gcc.target/aarch64/ssadv16qi.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O3" } */ +#pragma GCC target "+nosve" + #define N 1024 signed char pix1[N], pix2[N]; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c new file mode 100644 index 00000000000..03ebe2554fb --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/abs_1.c @@ -0,0 +1,21 @@ +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O3 --save-temps" } */ + +#include + +#define DO_OPS(TYPE) \ +void vneg_##TYPE (TYPE *dst, TYPE *src, int count) \ +{ \ + for (int i = 0; i < count; ++i) \ + dst[i] = src[i] < 0 ? -src[i] : src[i]; \ +} + +DO_OPS (int8_t) +DO_OPS (int16_t) +DO_OPS (int32_t) +DO_OPS (int64_t) + +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.b, p[0-7]/m, z[0-9]+\.b\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.h, p[0-7]/m, z[0-9]+\.h\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.s, p[0-7]/m, z[0-9]+\.s\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tabs\tz[0-9]+\.d, p[0-7]/m, z[0-9]+\.d\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/usadv16qi.c b/gcc/testsuite/gcc.target/aarch64/usadv16qi.c index b7c08ee1e11..69ceaf4259e 100644 --- a/gcc/testsuite/gcc.target/aarch64/usadv16qi.c +++ b/gcc/testsuite/gcc.target/aarch64/usadv16qi.c @@ -1,6 +1,8 @@ /* { dg-do compile } */ /* { dg-options "-O3" } */ +#pragma GCC target "+nosve" + #define N 1024 unsigned char pix1[N], pix2[N]; diff --git a/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c b/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c index 19082d73ea8..8d4bf2a5d39 100644 --- a/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c +++ b/gcc/testsuite/gcc.target/aarch64/vect-abs-compile.c @@ -1,7 +1,8 @@ - /* { dg-do compile } */ /* { dg-options "-O3 -fno-vect-cost-model" } */ +#pragma GCC target "+nosve" + #define N 16 #include "vect-abs.x" -- 2.30.2