From 69c6aadb4d61a0c6242d1d250d9db4d6cb3664db Mon Sep 17 00:00:00 2001 From: Xan Date: Wed, 25 Apr 2018 05:53:37 +0100 Subject: [PATCH] --- Harmonised_RVV/Packed_SIMD.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn index f720761a9..75d7b3c8c 100644 --- a/Harmonised_RVV/Packed_SIMD.mdwn +++ b/Harmonised_RVV/Packed_SIMD.mdwn @@ -34,7 +34,7 @@ Notes: The default RVV MVL value (in absence of explicit VDCFG setup) is to be MVL = 2 on RV32I machines and MVL = 4 on RV64I machines. However, note RV32I registers can fit 4x INT8 elements. To preserve Andes SIMD behaviour, all VOP instructions should still operate on all “unused” elements in the register, regardless of MVL. (This is still compliant with the RVV spec, provided elements from VL..MVL-1 are set to zero). VMEM instructions however will only operate on VL elements, and so where full Andes SIMD compliance is required (without RVV forward compatibility), LW/LD and SW/SD are to be used instead of VLD and VST. -##### Alternative register "banks" and MVL +##### Alternative register "banks" and alternative MVL A programmer can configure VCFG with the any mix of these alternative configurations: -- 2.30.2