From 69e4e88689965a1c2956ae874bca5676144a366c Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 12:46:58 +0100
Subject: [PATCH] tidyup

---
 src/ieee754/fpcommon/roundz.py | 51 +++++++---------------------------
 1 file changed, 10 insertions(+), 41 deletions(-)

diff --git a/src/ieee754/fpcommon/roundz.py b/src/ieee754/fpcommon/roundz.py
index 3a656459..4613a008 100644
--- a/src/ieee754/fpcommon/roundz.py
+++ b/src/ieee754/fpcommon/roundz.py
@@ -2,13 +2,13 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Elaboratable
+from nmigen import Module, Signal
 from nmigen.cli import main, verilog
 
+from ieee754.fpcommon.modbase import FPModBase
 from ieee754.fpcommon.fpbase import FPNumBase, FPNumBaseRecord
-from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.getop import FPPipeContext
-from .postnormalise import FPNorm1Data
+from ieee754.fpcommon.postnormalise import FPNorm1Data
 
 
 class FPRoundData:
@@ -28,12 +28,10 @@ class FPRoundData:
         return ret
 
 
-class FPRoundMod(Elaboratable):
+class FPRoundMod(FPModBase):
 
     def __init__(self, pspec):
-        self.pspec = pspec
-        self.i = self.ispec()
-        self.out_z = self.ospec()
+        super().__init__(pspec, "roundz")
 
     def ispec(self):
         return FPNorm1Data(self.pspec)
@@ -41,47 +39,18 @@ class FPRoundMod(Elaboratable):
     def ospec(self):
         return FPRoundData(self.pspec)
 
-    def process(self, i):
-        return self.out_z
-
-    def setup(self, m, i):
-        m.submodules.roundz = self
-        m.d.comb += self.i.eq(i)
-
     def elaborate(self, platform):
         m = Module()
-        m.d.comb += self.out_z.eq(self.i)  # copies muxid, z, out_do_z
+        comb = m.d.comb
+
+        comb += self.o.eq(self.i)  # copies muxid, z, out_do_z
         with m.If(~self.i.out_do_z):  # bypass wasn't enabled
             with m.If(self.i.roundz):
-                m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1)  # mantissa up
+                comb += self.o.z.m.eq(self.i.z.m + 1)  # mantissa up
                 with m.If(self.i.z.m == self.i.z.m1s):  # all 1s
                     # exponent up
-                    m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1)
+                    comb += self.o.z.e.eq(self.i.z.e + 1)
 
         return m
 
 
-class FPRound(FPState):
-
-    def __init__(self, width, id_wid):
-        FPState.__init__(self, "round")
-        self.mod = FPRoundMod(width)
-        self.out_z = self.ospec()
-
-    def ispec(self):
-        return self.mod.ispec()
-
-    def ospec(self):
-        return self.mod.ospec()
-
-    def setup(self, m, i):
-        """ links module to inputs and outputs
-        """
-        self.mod.setup(m, i)
-
-        self.idsync(m)
-        m.d.sync += self.out_z.eq(self.mod.out_z)
-        m.d.sync += self.out_z.ctx.eq(self.mod.o.ctx)
-
-    def action(self, m):
-        m.next = "corrections"
-- 
2.30.2