From 69e5334183da058d8d5f7b13620c8ce09270d937 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 27 Jun 2019 23:19:43 +0100 Subject: [PATCH] --- simple_v_extension/abridged_spec.mdwn | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn index c0edc7beb..6d707b5ed 100644 --- a/simple_v_extension/abridged_spec.mdwn +++ b/simple_v_extension/abridged_spec.mdwn @@ -270,6 +270,13 @@ like Standard RISC-V as far as the instruction execution order is concerned, regardless of whether it is PC, PCVBLK, VL or SUBVL that is currently being incremented. +This.is extremely important. Exceptions +**MUST** be raised one at a time and in +strict sequential program order. + +No instructions are permitted to be out of +sequence, therefore no exceptions are permitted to be, either. + # Hints With Simple-V being capable of issuing *parallel* instructions where -- 2.30.2