From 69e869893d8dc48170bd3f4b08524fbf0f9db058 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 28 Feb 2015 11:36:15 +0100 Subject: [PATCH] remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future) --- make.py | 2 +- misoclib/com/liteeth/example_designs/targets/base.py | 8 ++++---- .../mem/litesata/example_designs/targets/bist.py | 8 ++++---- misoclib/{gensoc => soc}/__init__.py | 12 ++++++------ misoclib/{gensoc => soc}/cpuif.py | 0 .../litescope/example_designs/targets/simple.py | 8 ++++---- targets/de0nano.py | 2 +- targets/kc705.py | 2 +- targets/mlabs_video.py | 2 +- targets/pipistrello.py | 2 +- targets/ppro.py | 2 +- targets/simple.py | 6 +++--- 12 files changed, 27 insertions(+), 27 deletions(-) rename misoclib/{gensoc => soc}/__init__.py (97%) rename misoclib/{gensoc => soc}/cpuif.py (100%) diff --git a/make.py b/make.py index 470a23a9..3153404b 100755 --- a/make.py +++ b/make.py @@ -6,7 +6,7 @@ from mibuild.tools import write_to_file from migen.util.misc import autotype from migen.fhdl import simplify -from misoclib.gensoc import cpuif +from misoclib.soc import cpuif from misoclib.cpu import CPU from misoclib.mem.sdram.phy import initsequence diff --git a/misoclib/com/liteeth/example_designs/targets/base.py b/misoclib/com/liteeth/example_designs/targets/base.py index 784e4762..ef099ade 100644 --- a/misoclib/com/liteeth/example_designs/targets/base.py +++ b/misoclib/com/liteeth/example_designs/targets/base.py @@ -55,7 +55,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), ] -class GenSoC(Module): +class SoC(Module): csr_base = 0x00000000 csr_data_width = 32 csr_map = { @@ -109,17 +109,17 @@ class GenSoC(Module): for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) -class BaseSoC(GenSoC, AutoCSR): +class BaseSoC(SoC, AutoCSR): default_platform = "kc705" csr_map = { "phy": 11, "core": 12 } - csr_map.update(GenSoC.csr_map) + csr_map.update(SoC.csr_map) def __init__(self, platform, clk_freq=166*1000000, mac_address=0x10e2d5000000, ip_address="192.168.1.40"): - GenSoC.__init__(self, platform, clk_freq) + SoC.__init__(self, platform, clk_freq) self.submodules.crg = _CRG(platform) # wishbone SRAM (to test Wishbone over UART and Etherbone) diff --git a/misoclib/mem/litesata/example_designs/targets/bist.py b/misoclib/mem/litesata/example_designs/targets/bist.py index 2a8285a1..07cce1b1 100644 --- a/misoclib/mem/litesata/example_designs/targets/bist.py +++ b/misoclib/mem/litesata/example_designs/targets/bist.py @@ -55,7 +55,7 @@ class _CRG(Module): AsyncResetSynchronizer(self.cd_sys, ~pll_locked | platform.request("cpu_reset") | self.reset), ] -class GenSoC(Module): +class SoC(Module): csr_base = 0x00000000 csr_data_width = 32 csr_map = { @@ -130,15 +130,15 @@ class BISTLeds(Module): self.comb += platform.request("user_led", 2).eq(sata_phy.crg.ready) self.comb += platform.request("user_led", 3).eq(sata_phy.ctrl.ready) -class BISTSoC(GenSoC, AutoCSR): +class BISTSoC(SoC, AutoCSR): default_platform = "kc705" csr_map = { "sata": 10, } - csr_map.update(GenSoC.csr_map) + csr_map.update(SoC.csr_map) def __init__(self, platform): clk_freq = 166*1000000 - GenSoC.__init__(self, platform, clk_freq) + SoC.__init__(self, platform, clk_freq) self.submodules.crg = _CRG(platform) # SATA PHY/Core/Frontend diff --git a/misoclib/gensoc/__init__.py b/misoclib/soc/__init__.py similarity index 97% rename from misoclib/gensoc/__init__.py rename to misoclib/soc/__init__.py index 3ce45252..28071461 100644 --- a/misoclib/gensoc/__init__.py +++ b/misoclib/soc/__init__.py @@ -17,7 +17,7 @@ from misoclib.mem.sdram import memtest def mem_decoder(address, start=26, end=29): return lambda a: a[start:end] == ((address >> (start+2)) & (2**(end-start))-1) -class GenSoC(Module): +class SoC(Module): csr_map = { "crg": 0, # user "uart": 1, # provided by default (optional) @@ -160,7 +160,7 @@ class GenSoC(Module): if isinstance(self.cpu_or_bridge, CPU): for mem in ["rom", "sram"]: if mem not in registered_mems: - raise FinalizeError("CPU needs a {} to be registered with GenSoC.register_mem()".format(mem)) + raise FinalizeError("CPU needs a {} to be registered with SoC.register_mem()".format(mem)) # Wishbone self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters, @@ -192,7 +192,7 @@ class GenSoC(Module): def do_exit(self, vns): pass -class SDRAMSoC(GenSoC): +class SDRAMSoC(SoC): csr_map = { "dfii": 6, "lasmicon": 7, @@ -200,14 +200,14 @@ class SDRAMSoC(GenSoC): "memtest_w": 9, "memtest_r": 10 } - csr_map.update(GenSoC.csr_map) + csr_map.update(SoC.csr_map) def __init__(self, platform, clk_freq, ramcon_type="lasmicon", with_l2=True, l2_size=8192, with_memtest=False, **kwargs): - GenSoC.__init__(self, platform, clk_freq, **kwargs) + SoC.__init__(self, platform, clk_freq, **kwargs) self.ramcon_type = ramcon_type self.with_l2 = with_l2 @@ -268,4 +268,4 @@ class SDRAMSoC(GenSoC): def do_finalize(self): if not self._sdram_phy_registered: raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()") - GenSoC.do_finalize(self) + SoC.do_finalize(self) diff --git a/misoclib/gensoc/cpuif.py b/misoclib/soc/cpuif.py similarity index 100% rename from misoclib/gensoc/cpuif.py rename to misoclib/soc/cpuif.py diff --git a/misoclib/tools/litescope/example_designs/targets/simple.py b/misoclib/tools/litescope/example_designs/targets/simple.py index 95a81e50..a282ffe8 100644 --- a/misoclib/tools/litescope/example_designs/targets/simple.py +++ b/misoclib/tools/litescope/example_designs/targets/simple.py @@ -27,7 +27,7 @@ class _CRG(Module): self.cd_sys.rst.eq(~rst_n) ] -class GenSoC(Module): +class SoC(Module): csr_base = 0x00000000 csr_data_width = 32 csr_map = { @@ -71,16 +71,16 @@ class GenSoC(Module): for name, memory, mapaddr, mmap in self.csrbankarray.srams: self.add_cpu_csr_region(name, 0xe0000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory) -class LiteScopeSoC(GenSoC, AutoCSR): +class LiteScopeSoC(SoC, AutoCSR): default_platform = "de0nano" csr_map = { "io": 10, "la": 11 } - csr_map.update(GenSoC.csr_map) + csr_map.update(SoC.csr_map) def __init__(self, platform): clk_freq = 50*1000000 - GenSoC.__init__(self, platform, clk_freq) + SoC.__init__(self, platform, clk_freq) self.submodules.crg = _CRG(platform.request("clk50")) self.submodules.io = LiteScopeIO(8) diff --git a/targets/de0nano.py b/targets/de0nano.py index 13217709..3062cb3c 100644 --- a/targets/de0nano.py +++ b/targets/de0nano.py @@ -5,7 +5,7 @@ from misoclib.cpu.peripherals import gpio from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy from misoclib.com import uart -from misoclib.gensoc import SDRAMSoC +from misoclib.soc import SDRAMSoC class _PLL(Module): def __init__(self, period_in, name, phase_shift, operation_mode): diff --git a/targets/kc705.py b/targets/kc705.py index a8fd017e..532b1365 100644 --- a/targets/kc705.py +++ b/targets/kc705.py @@ -4,7 +4,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import k7ddrphy from misoclib.mem.flash import spiflash -from misoclib.gensoc import SDRAMSoC, mem_decoder +from misoclib.soc import SDRAMSoC, mem_decoder from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII from misoclib.com.liteeth.mac import LiteEthMAC diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py index 8ff171f3..fe8bf1b2 100644 --- a/targets/mlabs_video.py +++ b/targets/mlabs_video.py @@ -10,7 +10,7 @@ from misoclib.mem.sdram.phy import s6ddrphy from misoclib.mem.flash import norflash16 from misoclib.cpu.peripherals import gpio from misoclib.video import framebuffer -from misoclib.gensoc import SDRAMSoC, mem_decoder +from misoclib.soc import SDRAMSoC, mem_decoder from misoclib.com.liteeth.phy.mii import LiteEthPHYMII from misoclib.com.liteeth.mac import LiteEthMAC diff --git a/targets/pipistrello.py b/targets/pipistrello.py index 39ce3c8c..8c27d78b 100644 --- a/targets/pipistrello.py +++ b/targets/pipistrello.py @@ -6,7 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.flash import SpiFlash -from misoclib.gensoc import SDRAMSoC +from misoclib.soc import SDRAMSoC class _CRG(Module): def __init__(self, platform, clk_freq): diff --git a/targets/ppro.py b/targets/ppro.py index 3303c453..e9108344 100644 --- a/targets/ppro.py +++ b/targets/ppro.py @@ -6,7 +6,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from misoclib.mem import sdram from misoclib.mem.sdram.phy import gensdrphy from misoclib.mem.flash import spiflash -from misoclib.gensoc import SDRAMSoC +from misoclib.soc import SDRAMSoC class _CRG(Module): def __init__(self, platform, clk_freq): diff --git a/targets/simple.py b/targets/simple.py index 02b23385..32c72ffb 100644 --- a/targets/simple.py +++ b/targets/simple.py @@ -1,7 +1,7 @@ from migen.fhdl.std import * from migen.bus import wishbone -from misoclib.gensoc import GenSoC, mem_decoder +from misoclib.soc import SoC, mem_decoder class _CRG(Module): def __init__(self, clk_in): @@ -17,9 +17,9 @@ class _CRG(Module): self.cd_sys.rst.eq(~rst_n) ] -class SimpleSoC(GenSoC): +class SimpleSoC(SoC): def __init__(self, platform, **kwargs): - GenSoC.__init__(self, platform, + SoC.__init__(self, platform, clk_freq=int((1/(platform.default_clk_period))*1000000000), with_rom=True, with_sdram=True, sdram_size=16*1024, -- 2.30.2