From 69f003531531900f78e0c19dd9d933d0903ed38f Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 29 Apr 2016 23:03:43 +0200
Subject: [PATCH] gen/fhdl: add Display for debug in simulation

---
 litex/gen/fhdl/structure.py | 5 +++++
 litex/gen/fhdl/verilog.py   | 9 +++++++++
 2 files changed, 14 insertions(+)

diff --git a/litex/gen/fhdl/structure.py b/litex/gen/fhdl/structure.py
index 959b6ce9..60bd2b8b 100644
--- a/litex/gen/fhdl/structure.py
+++ b/litex/gen/fhdl/structure.py
@@ -718,3 +718,8 @@ class _Fragment:
         self.specials |= other.specials
         self.clock_domains += other.clock_domains
         return self
+
+class Display:
+    def __init__(self, s, *args):
+        self.s = s
+        self.args = args
diff --git a/litex/gen/fhdl/verilog.py b/litex/gen/fhdl/verilog.py
index 78a0aa88..4a647dd1 100644
--- a/litex/gen/fhdl/verilog.py
+++ b/litex/gen/fhdl/verilog.py
@@ -118,6 +118,15 @@ def _printexpr(ns, node):
 def _printnode(ns, at, level, node):
     if node is None:
         return ""
+    elif isinstance(node, Display):
+        s = "\"" + node.s + "\\r\""
+        for arg in node.args:
+            s += ", "
+            if isinstance(arg, Signal):
+                s += ns.get_name(arg)
+            else:
+                s += str(arg)
+        return "\t"*level + "$display(" + s + ");\n"
     elif isinstance(node, _Assign):
         if at == _AT_BLOCKING:
             assignment = " = "
-- 
2.30.2