From 69fb4c97a2646e73bdaced6f5b50125ac0feadd2 Mon Sep 17 00:00:00 2001
From: "colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0"
 <colepoirier@1ec9c8c87c85f09e4718cd80e0605065e33975f0@web>
Date: Wed, 29 Jul 2020 19:16:41 +0100
Subject: [PATCH]

---
 cole.mdwn | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/cole.mdwn b/cole.mdwn
index 1cbb26f8c..0786f8b8a 100644
--- a/cole.mdwn
+++ b/cole.mdwn
@@ -13,13 +13,9 @@ move things along from one stage to the next
 - <https://bugs.libre-soc.org/show_bug.cgi?id=375> Recruiting more engineers to the project
 - <https://bugs.libre-soc.org/show_bug.cgi?id=380> First round of recruitment attempts
 - <https://bugs.libre-soc.org/show_bug.cgi?id=379> Create wiki page for recruitment emails to point to
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=388> bpermd tutorial 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=389> Create bug report for each diagram to be converted to SVG 
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=394> Contact 'BlackParrot' RV64GC Multicore SoC devs
-
 - <https://bugs.libre-soc.org/show_bug.cgi?id=442> Convert comp_unit_req_rel diagram to SVG
 
 ## List of things that need more fleshed out bug reports:
@@ -27,9 +23,11 @@ move things along from one stage to the next
 - Scoreboard documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
+
 - LDST documentation
   - <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008287.html>
 
+
 ## Completed but not yet submitted
 
 - <https://bugs.libre-soc.org/show_bug.cgi?id=401> Convert 180nm Test ASIC Mem Layout diagram to SVG 
-- 
2.30.2