From 6a16c3d153da91a658bc70b9a1af0bbd52e982c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 23 Jul 2020 22:41:19 +0100 Subject: [PATCH] allow imem to be 64/32 bit wide --- src/soc/minerva/units/fetch.py | 7 +++++-- src/soc/simple/issuer.py | 6 +++++- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py index 74d6d8e6..20221275 100644 --- a/src/soc/minerva/units/fetch.py +++ b/src/soc/minerva/units/fetch.py @@ -12,8 +12,11 @@ class FetchUnitInterface: def __init__(self, pspec): self.pspec = pspec self.addr_wid = pspec.addr_wid - self.data_wid = pspec.reg_wid - self.adr_lsbs = log2_int(pspec.reg_wid//8) + if isinstance(pspec.imem_reg_wid, int): + self.data_wid = pspec.imem_reg_wid + else: + self.data_wid = pspec.reg_wid + self.adr_lsbs = log2_int(self.data_wid//8) self.ibus = Record(make_wb_layout(pspec)) bad_wid = pspec.addr_wid - self.adr_lsbs # TODO: is this correct? diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 1b8d82eb..9de80a51 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -150,7 +150,11 @@ class TestIssuer(Elaboratable): comb += self.imem.f_valid_i.eq(1) with m.Else(): # not busy: instruction fetched - insn = self.imem.f_instr_o.word_select(cur_pc[2], 32) + f_instr_o = self.imem.f_instr_o + if f_instr_o.width == 32: + insn = f_instr_o + else: + insn = f_instr_o.word_select(cur_pc[2], 32) comb += current_insn.eq(insn) comb += core_ivalid_i.eq(1) # instruction is valid comb += core_issue_i.eq(1) # and issued -- 2.30.2