From 6a36e901d39731b965f2eda19977ddf8641c0f58 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 5 May 2019 21:14:26 +0100 Subject: [PATCH] slightly simplify SRlatch --- src/nmutil/latch.py | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py index 41a8df94..a334f667 100644 --- a/src/nmutil/latch.py +++ b/src/nmutil/latch.py @@ -20,20 +20,20 @@ class SRLatch(Elaboratable): m.d.sync += q_int.eq(1) with m.Elif(self.r): m.d.sync += q_int.eq(0) + with m.Else(): + m.d.sync += q_int.eq(q_int) m.d.comb += self.q.eq(q_int) - m.d.comb += self.qn.eq(~q_int) else: with m.If(self.s): m.d.sync += q_int.eq(1) m.d.comb += self.q.eq(1) - m.d.comb += self.qn.eq(0) with m.Elif(self.r): m.d.sync += q_int.eq(0) m.d.comb += self.q.eq(0) - m.d.comb += self.qn.eq(1) with m.Else(): + m.d.sync += q_int.eq(q_int) m.d.comb += self.q.eq(q_int) - m.d.comb += self.qn.eq(~q_int) + m.d.comb += self.qn.eq(~self.q) return m @@ -72,5 +72,12 @@ def test_sr(): run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch.vcd') + dut = SRLatch(sync=False) + vl = rtlil.convert(dut, ports=dut.ports()) + with open("test_srlatch_async.il", "w") as f: + f.write(vl) + + run_simulation(dut, sr_sim(dut), vcd_name='test_srlatch_async.vcd') + if __name__ == '__main__': test_sr() -- 2.30.2