From 6a48baf8069bfc0d37d051a997ffe4cd9da268e8 Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 3 May 2016 12:24:25 -0700 Subject: [PATCH] Remove unused code. Add some debug printfs, which I'll be wanting for at least a little while. --- riscv/encoding.h | 2 ++ riscv/gdbserver.cc | 21 --------------------- riscv/mmu.cc | 4 ++++ riscv/processor.cc | 3 ++- 4 files changed, 8 insertions(+), 22 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index ea45e54..11aa518 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -33,6 +33,8 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 +#define DCSR_PRV (3<<14) + #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) diff --git a/riscv/gdbserver.cc b/riscv/gdbserver.cc index 113d10d..3a4d199 100644 --- a/riscv/gdbserver.cc +++ b/riscv/gdbserver.cc @@ -288,27 +288,6 @@ class halt_op_t : public operation_t gs.saved_mcause = ((uint64_t) gs.read_debug_ram(1) << 32) | gs.read_debug_ram(0); gs.saved_mstatus = ((uint64_t) gs.read_debug_ram(3) << 32) | gs.read_debug_ram(2); gs.dcsr = ((uint64_t) gs.read_debug_ram(5) << 32) | gs.read_debug_ram(4); - -#if 0 - // TODO: This scheme doesn't work, because we're unable to write to eg. - // 0x108 to clear debug int with mstatus configured this way. - - // Set mstatus.mprv, and mstatus.mpp to dcsr.prv. - // This ensures that memory accesses act as they would in whatever mode - // the processor was in when we interrupted it. A fancier debugger - // might walk page tables itself and perform its own address - // translation. - reg_t mstatus = gs.saved_mstatus; - mstatus = set_field(mstatus, MSTATUS_MPRV, 1); - mstatus = set_field(mstatus, MSTATUS_MPP, get_field(gs.dcsr, DCSR_PRV)); - gs.write_debug_ram(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16)); - gs.write_debug_ram(1, csrw(S0, CSR_MSTATUS)); - gs.write_debug_ram(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2)))); - gs.write_debug_ram(4, mstatus); - gs.write_debug_ram(5, mstatus >> 32); - gs.set_interrupt(0); - state = WRITE_MSTATUS; -#endif return true; } } diff --git a/riscv/mmu.cc b/riscv/mmu.cc index dee41a9..df6770f 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -44,6 +44,8 @@ reg_t mmu_t::translate(reg_t addr, access_type type) if (get_field(proc->state.mstatus, MSTATUS_VM) == VM_MBARE) mode = PRV_M; + fprintf(stderr, "translate(0x%lx, %d), mstatus=0x%lx, prv=%ld, mode=%ld, pum=%d\n", + addr, type, proc->state.mstatus, proc->state.prv, mode, pum); if (mode == PRV_M) { reg_t msb_mask = (reg_t(2) << (proc->xlen-1))-1; // zero-extend from xlen return addr & msb_mask; @@ -74,6 +76,7 @@ const uint16_t* mmu_t::fetch_slow_path(reg_t vaddr) void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes) { reg_t paddr = translate(addr, LOAD); + fprintf(stderr, "load_slow_path 0x%lx -> 0x%lx\n", addr, paddr); if (sim->addr_is_mem(paddr)) { memcpy(bytes, sim->addr_to_mem(paddr), len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, LOAD)) @@ -88,6 +91,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes) void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes) { reg_t paddr = translate(addr, STORE); + fprintf(stderr, "store_slow_path 0x%lx -> 0x%lx\n", addr, paddr); if (sim->addr_is_mem(paddr)) { memcpy(sim->addr_to_mem(paddr), bytes, len); if (tracer.interested_in_range(paddr, paddr + PGSIZE, STORE)) diff --git a/riscv/processor.cc b/riscv/processor.cc index f98d0a0..4c4e3dd 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -195,7 +195,7 @@ void processor_t::set_privilege(reg_t prv) void processor_t::enter_debug_mode(uint8_t cause) { - fprintf(stderr, "enter_debug_mode(%d)\n", cause); + fprintf(stderr, "enter_debug_mode(%d), mstatus=0x%lx, prv=0x%lx\n", cause, state.mstatus, state.prv); state.dcsr.cause = cause; state.dcsr.prv = state.prv; set_privilege(PRV_M); @@ -279,6 +279,7 @@ static bool validate_vm(int max_xlen, reg_t vm) void processor_t::set_csr(int which, reg_t val) { + fprintf(stderr, "set_csr(0x%x, 0x%lx)\n", which, val); val = zext_xlen(val); reg_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_COP); reg_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; -- 2.30.2