From 6a59f146dab21011087bc72acce68c24b65f6799 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 22 Dec 2021 03:53:45 +0000 Subject: [PATCH] when setting DSISR in LoadStore1 use correct load bit (from register) --- src/soc/fu/ldst/loadstore.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py index c31a84fc..3c96c9bc 100644 --- a/src/soc/fu/ldst/loadstore.py +++ b/src/soc/fu/ldst/loadstore.py @@ -250,7 +250,7 @@ class LoadStore1(PortInterfaceBase): sync += self.state.eq(State.IDLE) sync += ldst_r.eq(0) sync += Display("cache error -> update dsisr") - sync += self.dsisr[63 - 38].eq(~self.load) + sync += self.dsisr[63 - 38].eq(~ldst_r.load) # XXX there is no architected bit for this # (probably should be a machine check in fact) sync += self.dsisr[63 - 35].eq(d_in.cache_paradox) @@ -296,10 +296,9 @@ class LoadStore1(PortInterfaceBase): comb += exception.eq(1) comb += self.done.eq(1) sync += Display("MMU RADIX exception thrown") - sync += Display("TODO: notify MMU of change to dsisr") sync += self.dsisr[63 - 33].eq(m_in.invalid) sync += self.dsisr[63 - 36].eq(m_in.perm_error) # noexec - sync += self.dsisr[63 - 38].eq(~self.load) + sync += self.dsisr[63 - 38].eq(~ldst_r.load) sync += self.dsisr[63 - 44].eq(m_in.badtree) sync += self.dsisr[63 - 45].eq(m_in.rc_error) sync += self.state.eq(State.IDLE) -- 2.30.2