From 6a5a474362bd3206b7f7c92bbae0a71bea1aa06a Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Tue, 25 Oct 2022 16:34:29 +0100
Subject: [PATCH]

---
 openpower/sv/rfc/ls003.mdwn | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index f397365de..f7e97fd46 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -182,8 +182,8 @@ Pseudo-code:
 if ((RA) <u (RB)) & ((RB) != [0]*64) then  # Check RA<RB, for divide-by-0
     dividend[0:127] <- (RA) || (RC)        # Combine RA/RC as 128-bit
     divisor[0:127] <- [0]*64 || (RB)       # Extend RB to 128-bit
-    result <- dividend / divisor           # Division
-    modulo <- dividend % divisor           # Modulo
+    result <- dividend / divisor           # Unsigned Division
+    modulo <- dividend % divisor           # Unsigned Modulo
     RT <- result[64:127]                   # Store result in RT
     RS <- modulo[64:127]                   # Modulo in RC, implicit
 else                                       # In case of error
@@ -200,23 +200,24 @@ The 128-bit dividend is (RA) || (RC). The 64-bit divisor is
 placed into register RT. The modulo is placed into register RS.
 RS is implictly defined as the same register as RC, similarly to maddedu.
 
-The instruction is only defined where both conditions are true:
+The quotient can be represented in 64-bits when both these conditions
+are true:
 
 * (RA) < (RB) (unsigned comparison)
 * (RB) is NOT 0 (not divide-by-0)
 
 If these conditions are not met, RT is set to all 1's, RS to all 0's.
 
-Both operands, quotient, and modulo are interpreted as unsigned integers.
+All operands, quotient, and modulo are interpreted as unsigned integers.
 
-
-Divide/Modulo Quad-Double Unsigned is another VA-Form instruction
+Divide/Modulo Quad-Double Unsigned is a VA-Form instruction
 that is near-identical to `divdeu` except that:
 
 * the lower 64 bits of the dividend, instead of being zero, contain a
   register, RC.
 * it performs a fused divide and modulo in a single instruction, storing
   the modulo in an implicit RS (similar to `maddedu`)
+* There is no `UNDEFINED` behaviour.
 
 RB, the divisor, remains 64 bit.  The instruction is therefore a 128/64
 division, producing a (pair) of 64 bit result(s), in the same way that
-- 
2.30.2