From 6a66360b2a39a86c75036c65ea49f3899abd3bab Mon Sep 17 00:00:00 2001 From: Sandipan Das Date: Sat, 6 Feb 2021 17:17:57 +0530 Subject: [PATCH] arch-power: Add word divide-extended instructions This adds the following instructions. * Divide Word Extended (divwe[o][.]) * Divide Word Extended Unsigned (divweu[o][.]) Change-Id: Ie399269938c8e120ece667ce3fc9c6fe1d74faca Signed-off-by: Sandipan Das --- src/arch/power/isa/decoder.isa | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa index 4297d7d14..79fe314df 100644 --- a/src/arch/power/isa/decoder.isa +++ b/src/arch/power/isa/decoder.isa @@ -629,6 +629,44 @@ decode PO default Unknown::unknown() { } }}, true); + + 427: divwe({{ + int32_t src1 = Ra_sw; + int32_t src2 = Rb_sw; + int64_t res; + if ((src1 != INT32_MIN || src2 != -1) && src2 != 0) { + res = ((int64_t)src1 << 32) / src2; + if (res == (int32_t)res) { + Rt = (uint32_t)res; + } else { + Rt = 0; + setOV = true; + } + } else { + Rt = 0; + setOV = true; + } + }}, + true); + + 395: divweu({{ + uint32_t src1 = Ra_ud; + uint32_t src2 = Rb_ud; + uint64_t res; + if (src2 != 0) { + res = ((uint64_t)src1 << 32) / src2; + if (res <= UINT32_MAX) { + Rt = (uint32_t)res; + } else { + Rt = 0; + setOV = true; + } + } else { + Rt = 0; + setOV = true; + } + }}, + true); } default: decode XFX_XO { -- 2.30.2