From 6a79227deb29927ad71115ab99d9ff054173bd84 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 24 Aug 2022 04:35:10 -0700 Subject: [PATCH] fix translation of instructions that require Rc=True, like `sv.andi.` --- src/openpower/sv/trans/svp64.py | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 1b98b836..9a937798 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -664,7 +664,10 @@ class SVP64Asm: ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh") if v30b_op not in isa.instr: - raise Exception("opcode %s of '%s' not supported" % + if rc_mode and v30b_op + '.' in isa.instr: + v30b_op += '.' + else: + raise Exception("opcode %s of '%s' not supported" % (v30b_op, insn)) if ldst_shift: @@ -1350,7 +1353,9 @@ class SVP64Asm: log("fcoss", bin(insn)) yield ".long 0x%x" % insn else: - yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields)) + if not v30b_op.endswith('.'): + v30b_op += rc + yield "%s %s" % (v30b_op, ", ".join(v30b_newfields)) log("new v3.0B fields", v30b_op, v30b_newfields) def translate(self, lst): -- 2.30.2