From 6a979a8023516b1cc6b87c0b65d6aaa1fb22ce3d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 14 Mar 2015 00:10:08 +0100 Subject: [PATCH] mibuild: sanitize default clock management --- examples/cordic/cordic_impl.py | 8 ++++---- mibuild/altera/quartus.py | 1 + mibuild/crg.py | 14 -------------- mibuild/generic_platform.py | 22 ++++++++++++++-------- mibuild/platforms/apf27.py | 10 +--------- mibuild/platforms/apf51.py | 10 +--------- mibuild/platforms/de0nano.py | 10 +--------- mibuild/platforms/kc705.py | 11 ++--------- mibuild/platforms/lx9_microboard.py | 9 ++------- mibuild/platforms/m1.py | 9 ++------- mibuild/platforms/mixxeo.py | 9 ++------- mibuild/platforms/ml605.py | 10 +--------- mibuild/platforms/papilio_pro.py | 10 +--------- mibuild/platforms/pipistrello.py | 10 +--------- mibuild/platforms/rhino.py | 10 +--------- mibuild/platforms/sim.py | 1 - mibuild/platforms/usrp_b100.py | 12 ++---------- mibuild/platforms/zedboard.py | 10 +--------- mibuild/platforms/ztex_115d.py | 9 ++------- mibuild/xilinx/platform.py | 2 ++ migen/genlib/io.py | 19 +++++++++++++++++++ 21 files changed, 60 insertions(+), 146 deletions(-) delete mode 100644 mibuild/crg.py diff --git a/examples/cordic/cordic_impl.py b/examples/cordic/cordic_impl.py index f63418d1..594f2bda 100644 --- a/examples/cordic/cordic_impl.py +++ b/examples/cordic/cordic_impl.py @@ -5,7 +5,6 @@ from migen.fhdl.std import * from migen.genlib.cordic import Cordic from mibuild.tools import mkdir_noerror from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform class CordicImpl(Module): @@ -28,9 +27,11 @@ class CordicImpl(Module): self.platform.build(self, build_name=self.name) class Platform(XilinxPlatform): + default_clk_name = "clk" + default_clk_period = 20.0 + _io = [ ("clk", 0, Pins("AB13")), - ("rst", 0, Pins("V5")), ("do", 0, Pins("Y2 W3 W1 P8 P7 P6 P5 T4 T3", "U4 V3 N6 N7 M7 M8 R4 P4 M6 L6 P3 N4", @@ -38,8 +39,7 @@ class Platform(XilinxPlatform): ), ] def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io, - lambda p: SimpleCRG(p, "clk", "rst")) + XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", self._io) if __name__ == "__main__": default = dict(width=16, guard=0, eval_mode="pipelined", diff --git a/mibuild/altera/quartus.py b/mibuild/altera/quartus.py index 348596a5..b5468af0 100644 --- a/mibuild/altera/quartus.py +++ b/mibuild/altera/quartus.py @@ -94,5 +94,6 @@ class AlteraQuartusPlatform(GenericPlatform): return vns def add_period_constraint(self, clk, period): + # TODO: handle differential clk self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk) self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk) diff --git a/mibuild/crg.py b/mibuild/crg.py deleted file mode 100644 index 5d51a13b..00000000 --- a/mibuild/crg.py +++ /dev/null @@ -1,14 +0,0 @@ -from migen.fhdl.std import * - -class SimpleCRG(Module): - def __init__(self, platform, clk_name, rst_name, rst_invert=False): - reset_less = rst_name is None - self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less) - self._clk = platform.request(clk_name) - self.comb += self.cd_sys.clk.eq(self._clk) - - if not reset_less: - if rst_invert: - self.comb += self.cd_sys.rst.eq(~platform.request(rst_name)) - else: - self.comb += self.cd_sys.rst.eq(platform.request(rst_name)) diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index d8781e8a..4b4a6e3c 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -3,6 +3,7 @@ import os, sys from migen.fhdl.std import * from migen.fhdl.structure import _Fragment from migen.genlib.record import Record +from migen.genlib.io import CRG from migen.fhdl import verilog, edif from migen.util.misc import autotype @@ -177,10 +178,9 @@ class ConstraintManager: return self.platform_commands class GenericPlatform: - def __init__(self, device, io, default_crg_factory=None, connectors=[], name=None): + def __init__(self, device, io, connectors=[], name=None): self.device = device self.constraint_manager = ConstraintManager(io, connectors) - self.default_crg_factory = default_crg_factory if name is None: name = self.__module__.split(".")[-1] self.name = name @@ -194,6 +194,9 @@ class GenericPlatform: def lookup_request(self, *args, **kwargs): return self.constraint_manager.lookup_request(*args, **kwargs) + def add_period_constraint(self, clk, period): + raise NotImplementedError + def add_platform_command(self, *args, **kwargs): return self.constraint_manager.add_platform_command(*args, **kwargs) @@ -205,17 +208,20 @@ class GenericPlatform: raise ConstraintError("Already finalized") # if none exists, create a default clock domain and drive it if not fragment.clock_domains: - if self.default_crg_factory is None: - raise NotImplementedError("No clock/reset generator defined by either platform or user") - crg = self.default_crg_factory(self) + if not hasattr(self, "default_clk_name"): + raise NotImplementedError("No default clock and no clock domain defined") + crg = CRG(self.request(self.default_clk_name)) fragment += crg.get_fragment() self.do_finalize(fragment, *args, **kwargs) self.finalized = True def do_finalize(self, fragment, *args, **kwargs): - """overload this and e.g. add_platform_command()'s after the - modules had their say""" - pass + """overload this and e.g. add_platform_command()'s after the modules had their say""" + if hasattr(self, "default_clk_period"): + try: + self.add_period_constraint(self.lookup_request(self.default_clk_name), self.default_clk_period) + except ConstraintError: + pass def add_source(self, filename, language=None): if language is None: diff --git a/mibuild/platforms/apf27.py b/mibuild/platforms/apf27.py index 984dff36..fc2fe653 100644 --- a/mibuild/platforms/apf27.py +++ b/mibuild/platforms/apf27.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform _ios = [ @@ -146,11 +145,4 @@ class Platform(XilinxPlatform): default_clk_period = 10 def __init__(self): - XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, - lambda p: SimpleCRG(p, "clk0", None), _connectors) - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk0"), 10) - except ConstraintError: - pass + XilinxPlatform.__init__(self, "xc3s200a-ft256-4", _ios, _connectors) diff --git a/mibuild/platforms/apf51.py b/mibuild/platforms/apf51.py index 856f9921..d83dd16e 100644 --- a/mibuild/platforms/apf51.py +++ b/mibuild/platforms/apf51.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform _ios = [ @@ -173,11 +172,4 @@ class Platform(XilinxPlatform): default_clk_period = 10.526 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, - lambda p: SimpleCRG(p, "clk3", None), _connectors) - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk3"), 10.526) - except ConstraintError: - pass + XilinxPlatform.__init__(self, "xc6slx9-2csg225", _ios, _connectors) diff --git a/mibuild/platforms/de0nano.py b/mibuild/platforms/de0nano.py index 2ce73fc7..0e0fe326 100644 --- a/mibuild/platforms/de0nano.py +++ b/mibuild/platforms/de0nano.py @@ -2,7 +2,6 @@ # License: BSD from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.altera.quartus import AlteraQuartusPlatform from mibuild.altera.programmer import USBBlaster @@ -96,14 +95,7 @@ class Platform(AlteraQuartusPlatform): default_clk_period = 20 def __init__(self): - AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io, - lambda p: SimpleCRG(p, "clk50", None)) + AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io) def create_programmer(self): return USBBlaster() - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk50"), 20) - except ConstraintError: - pass diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py index 4d9e923f..b2df99d0 100644 --- a/mibuild/platforms/kc705.py +++ b/mibuild/platforms/kc705.py @@ -1,8 +1,6 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer from mibuild.xilinx.ise import XilinxISEToolchain -from mibuild.xilinx.common import CRG_DS _io = [ ("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")), @@ -383,9 +381,7 @@ class Platform(XilinxPlatform): default_clk_period = 6.4 def __init__(self, toolchain="vivado", programmer="xc3sprog"): - XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, - default_crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset"), - connectors=_connectors, + XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain=toolchain) self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4" self.programmer = programmer @@ -399,10 +395,7 @@ class Platform(XilinxPlatform): raise ValueError("{} programmer is not supported".format(programmer)) def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk156").p, 6.4) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) try: self.add_period_constraint(self.lookup_request("clk200").p, 5.0) except ConstraintError: diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py index e47a0f53..cbf03b3b 100644 --- a/mibuild/platforms/lx9_microboard.py +++ b/mibuild/platforms/lx9_microboard.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform _io = [ @@ -107,8 +106,7 @@ class Platform(XilinxPlatform): default_clk_period = 10 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io, - lambda p: SimpleCRG(p, "clk_y3", "user_btn")) + XilinxPlatform.__init__(self, "xc6slx9-2csg324", _io) self.add_platform_command(""" CONFIG VCCAUX = "3.3"; """) @@ -118,10 +116,7 @@ promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit """ def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk_y3"), 10) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) try: eth_clocks = self.lookup_request("eth_clocks") diff --git a/mibuild/platforms/m1.py b/mibuild/platforms/m1.py index 7884d3d9..8cd7fb19 100644 --- a/mibuild/platforms/m1.py +++ b/mibuild/platforms/m1.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform from mibuild.xilinx.programmer import UrJTAG @@ -124,17 +123,13 @@ class Platform(XilinxPlatform): default_clk_period = 20 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: SimpleCRG(p, "clk50", None)) + XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) def create_programmer(self): return UrJTAG("fjmem-m1.bit") def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk50"), 20) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) try: eth_clocks = self.lookup_request("eth_clocks") diff --git a/mibuild/platforms/mixxeo.py b/mibuild/platforms/mixxeo.py index e571f944..356f9883 100644 --- a/mibuild/platforms/mixxeo.py +++ b/mibuild/platforms/mixxeo.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform from mibuild.xilinx.programmer import UrJTAG @@ -160,18 +159,14 @@ class Platform(XilinxPlatform): default_clk_period = 20 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io, - lambda p: SimpleCRG(p, "clk50", None)) + XilinxPlatform.__init__(self, "xc6slx45-fgg484-2", _io) self.add_platform_command("CONFIG VCCAUX=\"3.3\";\n") def create_programmer(self): return UrJTAG("fjmem-mixxeo.bit") def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk50"), 20) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) try: eth_clocks = self.lookup_request("eth_clocks") diff --git a/mibuild/platforms/ml605.py b/mibuild/platforms/ml605.py index 1bdea3bf..ac4cf9f9 100644 --- a/mibuild/platforms/ml605.py +++ b/mibuild/platforms/ml605.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.xilinx.common import CRG_DS from mibuild.xilinx import XilinxPlatform _io = [ @@ -56,11 +55,4 @@ class Platform(XilinxPlatform): default_clk_period = 5 def __init__(self): - XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io, - lambda p: CRG_DS(p, "clk200", "user_btn")) - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk200").p, 5) - except ConstraintError: - pass + XilinxPlatform.__init__(self, "xc6vlx240t-ff1156-1", _io) diff --git a/mibuild/platforms/papilio_pro.py b/mibuild/platforms/papilio_pro.py index bd54ac51..2de08e94 100644 --- a/mibuild/platforms/papilio_pro.py +++ b/mibuild/platforms/papilio_pro.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform from mibuild.xilinx.programmer import XC3SProg @@ -55,14 +54,7 @@ class Platform(XilinxPlatform): default_clk_period = 31.25 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, - lambda p: SimpleCRG(p, "clk32", None), _connectors) + XilinxPlatform.__init__(self, "xc6slx9-tqg144-2", _io, _connectors) def create_programmer(self): return XC3SProg("papilio", "bscan_spi_lx9_papilio.bit") - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk32"), 31.25) - except ConstraintError: - pass diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py index 831285e8..dc9bebd4 100644 --- a/mibuild/platforms/pipistrello.py +++ b/mibuild/platforms/pipistrello.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform from mibuild.xilinx.programmer import XC3SProg @@ -130,14 +129,7 @@ class Platform(XilinxPlatform): default_clk_period = 20 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, - lambda p: SimpleCRG(p, "clk50", None), _connectors) + XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors) def create_programmer(self): return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit") - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk50"), 20.) - except ConstraintError: - pass diff --git a/mibuild/platforms/rhino.py b/mibuild/platforms/rhino.py index 77993cc7..cb2f043f 100644 --- a/mibuild/platforms/rhino.py +++ b/mibuild/platforms/rhino.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.xilinx.common import CRG_DS from mibuild.xilinx import XilinxPlatform _io = [ @@ -138,11 +137,4 @@ class Platform(XilinxPlatform): default_clk_period = 10 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io, - lambda p: CRG_DS(p, "clk100", "gpio")) - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk100").p, 10) - except ConstraintError: - pass + XilinxPlatform.__init__(self, "xc6slx150t-fgg676-3", _io) diff --git a/mibuild/platforms/sim.py b/mibuild/platforms/sim.py index 697edaa3..a0f83a5d 100644 --- a/mibuild/platforms/sim.py +++ b/mibuild/platforms/sim.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.sim.verilator import VerilatorPlatform class SimPins(Pins): diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py index be4b2130..ac2edb49 100644 --- a/mibuild/platforms/usrp_b100.py +++ b/mibuild/platforms/usrp_b100.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.xilinx.common import CRG_DS from mibuild.xilinx import XilinxPlatform _io = [ @@ -118,18 +117,11 @@ class Platform(XilinxPlatform): default_clk_period = 15.625 def __init__(self): - XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io, - lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True)) + XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io) self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp" def do_finalize(self, fragment): - try: - self.add_platform_command(""" -NET "{clk64}" TNM_NET = "GRPclk64"; -TIMESPEC "TSclk64" = PERIOD "GRPclk64" 15.625 ns HIGH 50%; -""", clk64=self.lookup_request("clk64")) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) self.add_platform_command(""" TIMESPEC TS_Pad2Pad = FROM PADS TO PADS 7 ns; diff --git a/mibuild/platforms/zedboard.py b/mibuild/platforms/zedboard.py index 74ba5d81..7be76018 100644 --- a/mibuild/platforms/zedboard.py +++ b/mibuild/platforms/zedboard.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform # Bank 34 and 35 voltage depend on J18 jumper setting @@ -142,11 +141,4 @@ class Platform(XilinxPlatform): default_clk_period = 10 def __init__(self): - XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, - lambda p: SimpleCRG(p, "clk100", None)) - - def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk100"), 10) - except ConstraintError: - pass + XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io) diff --git a/mibuild/platforms/ztex_115d.py b/mibuild/platforms/ztex_115d.py index a6880ef1..7b0a601d 100644 --- a/mibuild/platforms/ztex_115d.py +++ b/mibuild/platforms/ztex_115d.py @@ -1,5 +1,4 @@ from mibuild.generic_platform import * -from mibuild.crg import SimpleCRG from mibuild.xilinx import XilinxPlatform _io = [ @@ -86,17 +85,13 @@ class Platform(XilinxPlatform): default_clk_period = 20 def __init__(self): - XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io, - lambda p: SimpleCRG(p, "clk_if", "rst")) + XilinxPlatform.__init__(self, "xc6slx150-3csg484", _io) self.add_platform_command(""" CONFIG VCCAUX = "2.5"; """) def do_finalize(self, fragment): - try: - self.add_period_constraint(self.lookup_request("clk_if"), 20) - except ConstraintError: - pass + XilinxPlatform.do_finalize(self, fragment) try: clk_if = self.lookup_request("clk_if") diff --git a/mibuild/xilinx/platform.py b/mibuild/xilinx/platform.py index f5d3cd87..6ff6470d 100644 --- a/mibuild/xilinx/platform.py +++ b/mibuild/xilinx/platform.py @@ -36,4 +36,6 @@ class XilinxPlatform(GenericPlatform): return self.toolchain.build(self, *args, **kwargs) def add_period_constraint(self, clk, period): + if hasattr(clk, "p"): + clk = clk.p self.toolchain.add_period_constraint(self, clk, period) diff --git a/migen/genlib/io.py b/migen/genlib/io.py index 5e27eae3..67cef088 100644 --- a/migen/genlib/io.py +++ b/migen/genlib/io.py @@ -33,3 +33,22 @@ class DifferentialOutput(Special): @staticmethod def lower(dr): raise NotImplementedError("Attempted to use a differential output, but platform does not support them") + +class CRG(Module): + def __init__(self, clk): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_por = ClockDomain(reset_less=True) + + if hasattr(clk, "p"): + clk_se = Signal() + self.specials += DifferentialInput(clk.p, clk.n, clk_se) + clk = clk_se + + # Power on Reset (vendor agnostic) + rst_n = Signal() + self.sync.por += rst_n.eq(1) + self.comb += [ + self.cd_sys.clk.eq(clk), + self.cd_por.clk.eq(clk), + self.cd_sys.rst.eq(~rst_n) + ] -- 2.30.2