From 6aa2add6890c4af7b1714ae1fc6558c513c0d1e9 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sun, 26 Jan 2020 13:25:21 +0000
Subject: [PATCH]

---
 3d_gpu/architecture.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn
index ca20268e1..a201b8677 100644
--- a/3d_gpu/architecture.mdwn
+++ b/3d_gpu/architecture.mdwn
@@ -39,3 +39,7 @@ Section TODO, with own page [[architecture/memory_and_cache]]  LD/ST accesses ar
 # Bus arrangement
 
 Wishbone was chosen.  to expand why (related to patents).
+
+# IOMMU
+
+Section TODO, an IOMMU is an integral part of protecting processes from directly accessing peripherals (and other memory areas) that they shouldn't.
-- 
2.30.2