From 6ad0d585bfc28106f1fbea3273513add4a4fa1c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 21 Aug 2020 15:24:06 +0100 Subject: [PATCH] ld/st bus reduction test operational --- src/soc/bus/test/test_minerva.py | 5 +++-- src/soc/config/test/test_loadstore.py | 7 ++++--- src/soc/minerva/units/loadstore.py | 14 +++++++++++--- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/soc/bus/test/test_minerva.py b/src/soc/bus/test/test_minerva.py index 5d784b1f..9e34add2 100644 --- a/src/soc/bus/test/test_minerva.py +++ b/src/soc/bus/test/test_minerva.py @@ -7,15 +7,16 @@ from soc.minerva.units.fetch import BareFetchUnit, CachedFetchUnit class TestSRAMBareLoadStoreUnit(BareLoadStoreUnit): def __init__(self, pspec): super().__init__(pspec) + pspec = self.pspecslave # small 32-entry Memory if (hasattr(pspec, "dmem_test_depth") and isinstance(pspec.dmem_test_depth, int)): depth = pspec.dmem_test_depth else: - depth = 64 + depth = 32 print("TestSRAMBareLoadStoreUnit depth", depth) - self.mem = Memory(width=self.data_wid, depth=depth) + self.mem = Memory(width=pspec.reg_wid, depth=depth) def elaborate(self, platform): m = super().elaborate(platform) diff --git a/src/soc/config/test/test_loadstore.py b/src/soc/config/test/test_loadstore.py index 9b8884a4..02c491f9 100644 --- a/src/soc/config/test/test_loadstore.py +++ b/src/soc/config/test/test_loadstore.py @@ -24,6 +24,7 @@ def write_to_addr(dut, addr, value): yield dut.x_stall_i.eq(0) yield + yield yield dut.x_st_i.eq(0) while (yield dut.x_busy_o): yield @@ -82,8 +83,8 @@ def tst_lsmemtype(ifacetype): pspec = TestMemPspec(ldst_ifacetype=ifacetype, imem_ifacetype='', addr_wid=64, mask_wid=4, - wb_data_wid=32, - reg_wid=64) + wb_data_wid=16, + reg_wid=32) dut = ConfigLoadStoreUnit(pspec).lsi vl = rtlil.convert(dut, ports=[]) # TODOdut.ports()) with open("test_loadstore_%s.il" % ifacetype, "w") as f: @@ -96,7 +97,7 @@ def tst_lsmemtype(ifacetype): def process(): - values = [random.randint(0, 255) for x in range(16*4)] + values = [random.randint(0, 255) for x in range(0)] for addr, val in enumerate(values): yield from write_byte(dut, addr, val) x = yield from read_from_addr(dut, addr << 2) diff --git a/src/soc/minerva/units/loadstore.py b/src/soc/minerva/units/loadstore.py index 3526709d..3241e20e 100644 --- a/src/soc/minerva/units/loadstore.py +++ b/src/soc/minerva/units/loadstore.py @@ -15,13 +15,20 @@ __all__ = ["LoadStoreUnitInterface", "BareLoadStoreUnit", class LoadStoreUnitInterface: def __init__(self, pspec): self.pspec = pspec + self.pspecslave = pspec self.dbus = self.slavebus = Record(make_wb_layout(pspec)) print(self.dbus.sel.shape()) - if isinstance(pspec.wb_data_wid, int): + self.needs_cvt = False + if (hasattr(pspec, "dmem_test_depth") and + isinstance(pspec.wb_data_wid, int) and + pspec.wb_data_wid != pspec.reg_wid): pspecslave = deepcopy(pspec) pspecslave.reg_wid = pspec.wb_data_wid + mask_ratio = (pspec.reg_wid // pspec.wb_data_wid) + pspecslave.mask_wid = pspec.mask_wid // mask_ratio + self.pspecslave = pspecslave self.slavebus = Record(make_wb_layout(pspecslave)) - self.cvt = WishboneDownConvert(self.dbus, self.slavebus) + self.needs_cvt = True self.mask_wid = mask_wid = pspec.mask_wid self.addr_wid = addr_wid = pspec.addr_wid self.data_wid = data_wid = pspec.reg_wid @@ -87,7 +94,8 @@ class BareLoadStoreUnit(LoadStoreUnitInterface, Elaboratable): def elaborate(self, platform): m = Module() - if hasattr(self, "cvt"): + if self.needs_cvt: + self.cvt = WishboneDownConvert(self.dbus, self.slavebus) m.submodules.cvt = self.cvt with m.If(self.dbus.cyc): -- 2.30.2