From 6ad9571b172cd98099b477cba4efdd92c85bd222 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 9 Jan 2020 15:24:04 +0000 Subject: [PATCH] [AArch64] Rename UNSPEC_WHILE* to match instruction mnemonics The UNSPEC_WHILE*s had an underscore before the condition code, whereas almost all other SVE unspecs are taken directly from the mnemonic. 2020-01-09 Richard Sandiford gcc/ * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... (UNSPEC_WHILELE): ...this. (UNSPEC_WHILE_LO): Rename to... (UNSPEC_WHILELO): ...this. (UNSPEC_WHILE_LS): Rename to... (UNSPEC_WHILELS): ...this. (UNSPEC_WHILE_LT): Rename to... (UNSPEC_WHILELT): ...this. * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. (cmp_op, while_optab_cmp): Likewise. * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. (svwhilelt): Likewise. From-SVN: r280053 --- gcc/ChangeLog | 16 +++++++++++++++ .../aarch64/aarch64-sve-builtins-base.cc | 4 ++-- gcc/config/aarch64/aarch64.c | 2 +- gcc/config/aarch64/aarch64.md | 8 ++++---- gcc/config/aarch64/iterators.md | 20 +++++++++---------- 5 files changed, 33 insertions(+), 17 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ad7f519521c..e78cc37b537 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,19 @@ +2020-01-09 Richard Sandiford + + * config/aarch64/aarch64.md (UNSPEC_WHILE_LE): Rename to... + (UNSPEC_WHILELE): ...this. + (UNSPEC_WHILE_LO): Rename to... + (UNSPEC_WHILELO): ...this. + (UNSPEC_WHILE_LS): Rename to... + (UNSPEC_WHILELS): ...this. + (UNSPEC_WHILE_LT): Rename to... + (UNSPEC_WHILELT): ...this. + * config/aarch64/iterators.md (SVE_WHILE): Update accordingly. + (cmp_op, while_optab_cmp): Likewise. + * config/aarch64/aarch64.c (aarch64_sve_move_pred_via_while): Likewise. + * config/aarch64/aarch64-sve-builtins-base.cc (svwhilele): Likewise. + (svwhilelt): Likewise. + 2020-01-09 Richard Sandiford * config/aarch64/aarch64-sve-builtins-shapes.h (unary_count): Delete. diff --git a/gcc/config/aarch64/aarch64-sve-builtins-base.cc b/gcc/config/aarch64/aarch64-sve-builtins-base.cc index 10af6e9078d..e6145b498b7 100644 --- a/gcc/config/aarch64/aarch64-sve-builtins-base.cc +++ b/gcc/config/aarch64/aarch64-sve-builtins-base.cc @@ -2666,8 +2666,8 @@ FUNCTION (svunpkhi, svunpk_impl, (true)) FUNCTION (svunpklo, svunpk_impl, (false)) FUNCTION (svuzp1, svuzp_impl, (0)) FUNCTION (svuzp2, svuzp_impl, (1)) -FUNCTION (svwhilele, svwhile_impl, (UNSPEC_WHILE_LE, UNSPEC_WHILE_LS, true)) -FUNCTION (svwhilelt, svwhile_impl, (UNSPEC_WHILE_LT, UNSPEC_WHILE_LO, false)) +FUNCTION (svwhilele, svwhile_impl, (UNSPEC_WHILELE, UNSPEC_WHILELS, true)) +FUNCTION (svwhilelt, svwhile_impl, (UNSPEC_WHILELT, UNSPEC_WHILELO, false)) FUNCTION (svwrffr, svwrffr_impl,) FUNCTION (svzip1, svzip_impl, (0)) FUNCTION (svzip2, svzip_impl, (1)) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index afe41832857..e3bbf128736 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4272,7 +4272,7 @@ aarch64_sve_move_pred_via_while (rtx target, machine_mode mode, { rtx limit = force_reg (DImode, gen_int_mode (vl, DImode)); target = aarch64_target_reg (target, mode); - emit_insn (gen_while (UNSPEC_WHILE_LO, DImode, mode, + emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode, target, const0_rtx, limit)); return target; } diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 34cb99e2897..509b9e59b98 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -241,10 +241,10 @@ UNSPEC_UNPACKSLO UNSPEC_UNPACKULO UNSPEC_PACK - UNSPEC_WHILE_LE - UNSPEC_WHILE_LO - UNSPEC_WHILE_LS - UNSPEC_WHILE_LT + UNSPEC_WHILELE + UNSPEC_WHILELO + UNSPEC_WHILELS + UNSPEC_WHILELT UNSPEC_WHILERW UNSPEC_WHILEWR UNSPEC_LDN diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index dab3e4dac50..2c9d9660d24 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -2082,8 +2082,8 @@ (define_int_iterator SVE_CFP_TERNARY_LANE [UNSPEC_FCMLA UNSPEC_FCMLA90 UNSPEC_FCMLA180 UNSPEC_FCMLA270]) -(define_int_iterator SVE_WHILE [UNSPEC_WHILE_LE UNSPEC_WHILE_LO - UNSPEC_WHILE_LS UNSPEC_WHILE_LT]) +(define_int_iterator SVE_WHILE [UNSPEC_WHILELE UNSPEC_WHILELO + UNSPEC_WHILELS UNSPEC_WHILELT]) (define_int_iterator SVE2_WHILE_PTR [UNSPEC_WHILERW UNSPEC_WHILEWR]) @@ -2486,17 +2486,17 @@ (UNSPEC_COND_FCMLE "le") (UNSPEC_COND_FCMLT "lt") (UNSPEC_COND_FCMNE "ne") - (UNSPEC_WHILE_LE "le") - (UNSPEC_WHILE_LO "lo") - (UNSPEC_WHILE_LS "ls") - (UNSPEC_WHILE_LT "lt") + (UNSPEC_WHILELE "le") + (UNSPEC_WHILELO "lo") + (UNSPEC_WHILELS "ls") + (UNSPEC_WHILELT "lt") (UNSPEC_WHILERW "rw") (UNSPEC_WHILEWR "wr")]) -(define_int_attr while_optab_cmp [(UNSPEC_WHILE_LE "le") - (UNSPEC_WHILE_LO "ult") - (UNSPEC_WHILE_LS "ule") - (UNSPEC_WHILE_LT "lt")]) +(define_int_attr while_optab_cmp [(UNSPEC_WHILELE "le") + (UNSPEC_WHILELO "ult") + (UNSPEC_WHILELS "ule") + (UNSPEC_WHILELT "lt")]) (define_int_attr raw_war [(UNSPEC_WHILERW "raw") (UNSPEC_WHILEWR "war")]) -- 2.30.2