From 6adca6f1e1932557d9dcca07036b32f1b50e0079 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 1 Oct 2020 18:39:58 +0100 Subject: [PATCH] arg CacheRam read output needs delay by 1 cycle --- src/soc/experiment/dcache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index b3d0b76f..5f96e04a 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -1073,7 +1073,7 @@ class DCache(Elaboratable): wr_sel_m = Signal(ROW_SIZE) _d_out = Signal(WB_DATA_BITS, name="dout_%d" % i) - way = CacheRam(ROW_BITS, WB_DATA_BITS, True) + way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True) setattr(m.submodules, "cacheram_%d" % i, way) comb += way.rd_en.eq(do_read) -- 2.30.2