From 6b058515eaa368abef7536b924d7ed3319372d89 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 1 Jan 2023 15:09:21 +0000 Subject: [PATCH] enable misaligned Mem in ISACaller by default --- src/openpower/decoder/isa/caller.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index 0d93f05e..accce0c2 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1173,7 +1173,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop): self.last_op_svshape = False # "raw" memory - self.mem = Mem(row_bytes=8, initial_mem=initial_mem) + self.mem = Mem(row_bytes=8, initial_mem=initial_mem, misaligned_ok=True) self.mem.log_fancy(kind=LogKind.InstrInOuts) self.imem = Mem(row_bytes=4, initial_mem=initial_insns) # MMU mode, redirect underlying Mem through RADIX -- 2.30.2