From 6b15dd9695b0bb45670d20fc4cfe0c2959bc3697 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Apr 2022 13:56:50 +0100 Subject: [PATCH] --- openpower/sv/branches.mdwn | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index e1a0fe4e7..e340c9cb2 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -482,7 +482,8 @@ if LK then LR <-iea CIA + 4 Simplified pseudocode including LRu and CTR skipping, which illustrates clearly that SVP64 Scalar Branches (VL=1) are **not** identical to -v3.0B Scalar Branches. The key areas where differences occur are in +v3.0B Scalar Branches. The key areas where differences occur are +the inclusion of predication (which can still be used when VL=1), in when and why CTR is decremented (CTRtest Mode) and whether LR is updated (which is unconditional in v3.0B when LK=1, and conditional in SVP64 when LRu=1). @@ -492,11 +493,11 @@ if (mode_is_64bit) then M <- 0 else M <- 32 ctr_ok <- BO[2] | ((CTR[M:63] != 0) ^ BO[3]) cond_ok <- BO[0] | ¬(CR[BI+32] ^ BO[1]) -if ¬predicate_bit then cond_ok = SVRMmode.SNZ -ctrdec = ¬BO[2] -if CTRtest & (cond_ok ^ CTi) then - if ¬predicate_bit & ¬SVRMmode.sz then stop - ctrdec = 0b0 +if ¬predicate_bit then cond_ok = ctr_ok = SVRMmode.SNZ +if ¬predicate_bit & ¬SVRMmode.sz & ¬BO[2] & CTRtest & ¬CTI then + CTR = CTR - 1 + stop # instruction finishes here +ctrdec = ¬BO[2] & ¬(CTRtest & (cond_ok ^ CTi)) if ctrdec then CTR <- CTR - 1 lr_ok <- SVRMmode.LRu if ctr_ok & cond_ok then -- 2.30.2