From 6b2f7c78c78e9206aa9675cde7a8ef7d3dd0a285 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 9 Jun 2018 03:07:14 +0100 Subject: [PATCH] reorg --- simple_v_extension/simple_v_chennai_2018.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex index 6e1c4e5a8..24605fd68 100644 --- a/simple_v_extension/simple_v_chennai_2018.tex +++ b/simple_v_extension/simple_v_chennai_2018.tex @@ -472,11 +472,11 @@ for (i = 0; i < 16; i++) // 16 CSRs? tb[idx].regidx = CSRpred[i].regidx // indirection tb[idx].isvector = CSRpred[i].isvector tb[idx].packed = CSRpred[i].packed // SIMD or not - tb[idx].bank = CSRpred[i].bank // 0 (1=reserved) + tb[idx].bank = CSRpred[i].bank // 0 (1=rsvd) \end{semiverbatim} \begin{itemize} - \item All 64 (int and FP) Entries zero'd before setting + \item All 32 int (and 32 FP) entries zero'd before setup \item Might be a bit complex to set up (TBD) \end{itemize} -- 2.30.2