From 6b393aa8dda8104b1d19bb33660a56dff0138ffe Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 6 Jul 2020 20:19:26 +0100 Subject: [PATCH] add mullw test to qemu sim --- src/soc/simulator/test_mul_sim.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py index 9291207e..be95df68 100644 --- a/src/soc/simulator/test_mul_sim.py +++ b/src/soc/simulator/test_mul_sim.py @@ -30,6 +30,13 @@ class MulTestCases(FHDLTestCase): f"mullw 3, 1, 2"] self.run_tst_program(Program(lst), [3]) + def test_mullw(self): + lst = [f"addi 1, 0, 0x5678", + "neg 1, 1", + f"addi 2, 0, 0x1234", + f"mullw 3, 1, 2"] + self.run_tst_program(Program(lst), [3]) + def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None): initial_regs = [0] * 32 -- 2.30.2