From 6b6ccd10606c3c0811577e6edd5a95dbc46d17ba Mon Sep 17 00:00:00 2001 From: Richard Kenner Date: Mon, 11 Sep 1995 19:21:16 -0400 Subject: [PATCH] (float{,uns}sidf2): Call rs6000_float_const to portably build the proper floating point constant for conversions. (float{,uns}sidf2): Call rs6000_float_const to portably build the proper floating point constant for conversions. (movdi): Properly handle movdi of CONST_{INT,DOUBLE} on little endian systems. From-SVN: r10318 --- gcc/config/rs6000/rs6000.md | 35 ++++++++++++++++++++++++----------- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 70dd90db9a0..38bd4ba6818 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3338,9 +3338,7 @@ operands[2] = gen_reg_rtx (DImode); operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000); operands[4] = rs6000_immed_double_const (0, 0x43300000, DImode); - operands[5] = force_reg (DFmode, rs6000_immed_double_const (0x43300000, - 0x80000000, - DFmode)); + operands[5] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); }") (define_expand "floatunssidf2" @@ -3355,7 +3353,7 @@ { operands[2] = gen_reg_rtx (DImode); operands[3] = rs6000_immed_double_const (0, 0x43300000, DImode); - operands[4] = force_reg (DFmode, rs6000_immed_double_const (0x43300000, 0, DFmode)); + operands[4] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); }") ;; For the above two cases, we always split. @@ -4393,19 +4391,34 @@ "" " { + if (GET_CODE (operands[0]) == MEM) + operands[1] = force_reg (DImode, operands[1]); + if (GET_CODE (operands[1]) == CONST_DOUBLE || GET_CODE (operands[1]) == CONST_INT) { - emit_move_insn (operand_subword (operands[0], 0, 0, DImode), - operand_subword (operands[1], 0, 0, DImode)); - emit_move_insn (operand_subword (operands[0], 1, 0, DImode), - operand_subword (operands[1], 1, 0, DImode)); + HOST_WIDE_INT low; + HOST_WIDE_INT high; + + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + low = CONST_DOUBLE_LOW (operands[1]); + high = CONST_DOUBLE_HIGH (operands[1]); + } + else + { + low = INTVAL (operands[1]); + high = (low < 0) ? ~0 : 0; + } + + emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], WORDS_BIG_ENDIAN), + GEN_INT (low)); + + emit_move_insn (gen_rtx (SUBREG, SImode, operands[0], !WORDS_BIG_ENDIAN), + GEN_INT (high)); DONE; } - if (GET_CODE (operands[0]) == MEM) - operands[1] = force_reg (DImode, operands[1]); - /* Stores between FPR and any non-FPR registers must go through a temporary stack slot. */ -- 2.30.2