From 6b844da793861c21b8221db4c17370502b740601 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Tue, 13 Sep 2022 20:31:45 +0100 Subject: [PATCH] correct assrmbler in test_pysvpy4dis.py --- src/openpower/sv/trans/test_pysvp64dis.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index d730582b..977ec7d6 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -84,7 +84,6 @@ class SVSTATETestCase(unittest.TestCase): def test_7_batch(self): "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25" expected = [ - "addis 2,12,0", "addi 2,2,0", "addis 9,2,0", "addi 9,9,0", @@ -105,7 +104,7 @@ class SVSTATETestCase(unittest.TestCase): "sv.lfs *40,256(5)", "sv.fmuls *32,*32,*40", "sv.fsubs 0,0,*32", - "addi 4,4,65408", + "addi 4,4,-128", "stfs 0,0(6)", "add 6,6,7", "addi 4,4,4", @@ -134,16 +133,16 @@ class SVSTATETestCase(unittest.TestCase): "sv.fsubs 0,0,*40", "sv.fmuls *32,*32,*48", "sv.fsubs 1,1,*32", - "addi 4,4,65408", - "addi 16,16,65408", + "addi 4,4,-128", + "addi 16,16,-128", "stfs 0,0(6)", "add 6,6,7", "stfs 1,0(10)", "subf 10,7,10", "addi 8,8,4", "addi 4,4,4", - "addi 16,16,65532", - "bc 16,0,0xff4c", + "addi 16,16,-4", + "bc 16,0,-0xb4", "addi 5,3,128", "addi 4,4,128", "lfiwax 0,0,9", -- 2.30.2