From 6b85a4cdca82b820697ee07ac01d37673e26528d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 4 Sep 2020 20:56:44 +0100 Subject: [PATCH] add UART reserved IRQ @ 0 --- src/soc/litex/florent/sim.py | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 69a497b4..475314f2 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -37,6 +37,7 @@ class LibreSoCSim(SoCSDRAM): #sdram_data_width = 16, #sdram_module = "MT48LC16M16", sdram_data_width = 16, + irq_reserved_irqs = {'uart': 0}, ): assert cpu in ["libresoc", "microwatt"] platform = Platform() @@ -58,10 +59,10 @@ class LibreSoCSim(SoCSDRAM): #ram_fname = None #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ # "micropython/firmware.bin" - #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ - # "tests/xics/xics.bin" ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ - "hello_world/hello_world.bin" + "tests/xics/xics.bin" + #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ + # "hello_world/hello_world.bin" # reserve XICS ICP and XICS memory addresses. # TODO: not have these conflict with csr locations -- 2.30.2