From 6b9f90de789b1d0daf93ac1d2b608b057e7ca272 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 17:00:19 -0700
Subject: [PATCH] Fix typo

---
 kernel/rtlil.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 1d380135b..f42f5430f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
 	std::vector<RTLIL::Cell*> result;
-	result.reserve(wires_.size());
+	result.reserve(cells_.size());
 	for (auto &it : cells_)
 		if (design->selected(this, it.second))
 			result.push_back(it.second);
-- 
2.30.2