From 6bac9478c39fbe7955d10a21a2d7743697427a56 Mon Sep 17 00:00:00 2001 From: Eric Anholt Date: Wed, 3 Oct 2007 16:59:01 -0700 Subject: [PATCH] Replace duplicated intel_reg.h with a shared header. --- src/mesa/drivers/dri/i915/i915_reg.h | 2 - src/mesa/drivers/dri/i915/intel_batchbuffer.c | 2 +- src/mesa/drivers/dri/i915/intel_blit.c | 18 ++-- src/mesa/drivers/dri/i915/intel_context.h | 3 - src/mesa/drivers/dri/i965/intel_blit.c | 29 ++---- src/mesa/drivers/dri/i965/intel_reg.h | 95 ------------------- .../drivers/dri/{i915 => intel}/intel_reg.h | 60 +++++------- 7 files changed, 42 insertions(+), 167 deletions(-) delete mode 100644 src/mesa/drivers/dri/i965/intel_reg.h rename src/mesa/drivers/dri/{i915 => intel}/intel_reg.h (65%) diff --git a/src/mesa/drivers/dri/i915/i915_reg.h b/src/mesa/drivers/dri/i915/i915_reg.h index a9fa56e8a60..b5585e70e79 100644 --- a/src/mesa/drivers/dri/i915/i915_reg.h +++ b/src/mesa/drivers/dri/i915/i915_reg.h @@ -34,8 +34,6 @@ #define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) -#define CMD_3D (0x3<<29) - #define PRIM3D_INLINE (CMD_3D | (0x1f<<24)) #define PRIM3D_TRILIST (0x0<<18) #define PRIM3D_TRISTRIP (0x1<<18) diff --git a/src/mesa/drivers/dri/i915/intel_batchbuffer.c b/src/mesa/drivers/dri/i915/intel_batchbuffer.c index 045ff0a5b09..639457d44ab 100644 --- a/src/mesa/drivers/dri/i915/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i915/intel_batchbuffer.c @@ -28,7 +28,7 @@ #include "intel_batchbuffer.h" #include "intel_ioctl.h" #include "intel_decode.h" -#include "i915_debug.h" +#include "intel_reg.h" /* Relocations in kernel space: * - pass dma buffer seperately diff --git a/src/mesa/drivers/dri/i915/intel_blit.c b/src/mesa/drivers/dri/i915/intel_blit.c index 5d97f08434a..b00b0d9e1b5 100644 --- a/src/mesa/drivers/dri/i915/intel_blit.c +++ b/src/mesa/drivers/dri/i915/intel_blit.c @@ -105,8 +105,7 @@ intelCopyBuffer(const __DRIdrawablePrivate * dPriv, } else { BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = (XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); } for (i = 0; i < nbox; i++, pbox++) { @@ -184,8 +183,7 @@ intelEmitFillBlit(struct intel_context *intel, break; case 4: BR13 = dst_pitch | (0xF0 << 16) | (1 << 24) | (1 << 25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = (XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); break; default: return; @@ -273,8 +271,7 @@ intelEmitCopyBlit(struct intel_context *intel, (((GLint) dst_pitch) & 0xffff) | (translate_raster_op(logic_op) << 16) | (1 << 24) | (1 << 25); CMD = - (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + (XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB); break; default: return; @@ -443,15 +440,14 @@ intelClearWithBlit(GLcontext * ctx, GLbitfield mask) if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { CMD = XY_COLOR_BLT_CMD; if (clearMask & BUFFER_BIT_DEPTH) - CMD |= XY_COLOR_BLT_WRITE_RGB; + CMD |= XY_BLT_WRITE_RGB; if (clearMask & BUFFER_BIT_STENCIL) - CMD |= XY_COLOR_BLT_WRITE_ALPHA; + CMD |= XY_BLT_WRITE_ALPHA; } else { /* clearing RGBA */ - CMD = (XY_COLOR_BLT_CMD | - XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = XY_COLOR_BLT_CMD | + XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } } else { diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index 1e9ccd5cdc0..c8298dd9c43 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -460,9 +460,6 @@ extern void intelInitStateFuncs(struct dd_function_table *functions); #define BLENDFACT_INV_CONST_ALPHA 0x0f #define BLENDFACT_MASK 0x0f -#define MI_BATCH_BUFFER_END (0xA<<23) - - extern int intel_translate_compare_func(GLenum func); extern int intel_translate_stencil_op(GLenum op); extern int intel_translate_blend_factor(GLenum factor); diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index da6b68c22ba..962bb24f67a 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -110,8 +110,7 @@ void intelCopyBuffer( const __DRIdrawablePrivate *dPriv, } else { BR13 = (0xCC << 16) | (1<<24) | (1<<25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; } if (src->tiled) { @@ -199,8 +198,7 @@ void intelEmitFillBlit( struct intel_context *intel, break; case 4: BR13 = (0xF0 << 16) | (1<<24) | (1<<25); - CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: return; @@ -290,8 +288,7 @@ void intelEmitCopyBlit( struct intel_context *intel, case 4: BR13 = (translate_raster_op(logic_op) << 16) | (1<<24) | (1<<25); - CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA | - XY_SRC_COPY_BLT_WRITE_RGB); + CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; break; default: return; @@ -388,12 +385,11 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) break; case 4: BR13 = (0xF0 << 16) | (1<<24) | (1<<25); - BACK_CMD = FRONT_CMD = (XY_COLOR_BLT_CMD | - XY_COLOR_BLT_WRITE_ALPHA | - XY_COLOR_BLT_WRITE_RGB); + BACK_CMD = FRONT_CMD = XY_COLOR_BLT_CMD | + XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; DEPTH_CMD = XY_COLOR_BLT_CMD; - if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_COLOR_BLT_WRITE_RGB; - if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_COLOR_BLT_WRITE_ALPHA; + if (flags & BUFFER_BIT_DEPTH) DEPTH_CMD |= XY_BLT_WRITE_RGB; + if (flags & BUFFER_BIT_STENCIL) DEPTH_CMD |= XY_BLT_WRITE_ALPHA; break; default: return; @@ -517,11 +513,6 @@ void intelClearWithBlit(GLcontext *ctx, GLbitfield flags) } - -#define BR13_565 0x1 -#define BR13_8888 0x3 - - void intelEmitImmediateColorExpandBlit(struct intel_context *intel, GLuint cpp, @@ -576,15 +567,15 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel, opcode = XY_SETUP_BLT_CMD; if (cpp == 4) - opcode |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB; + opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; if (dst_tiled) opcode |= XY_DST_TILED; br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); if (cpp == 2) - br13 |= BR13_565 << 24; + br13 |= BR13_565; else - br13 |= BR13_8888 << 24; + br13 |= BR13_8888; BEGIN_BATCH(8, INTEL_BATCH_NO_CLIPRECTS); OUT_BATCH(opcode); diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h deleted file mode 100644 index 618afb6cbbb..00000000000 --- a/src/mesa/drivers/dri/i965/intel_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/************************************************************************** - * - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ - - -#ifndef _INTEL_REG_H_ -#define _INTEL_REG_H_ - - - -#define CMD_3D (0x3<<29) -#define CMD_2D (0x2<<29) - -#define _3DPRIMITIVE ((0x3<<29)|(0x1f<<24)) -#define PRIM_INDIRECT (1<<23) -#define PRIM_INLINE (0<<23) -#define PRIM_INDIRECT_SEQUENTIAL (0<<17) -#define PRIM_INDIRECT_ELTS (1<<17) - -#define PRIM3D_TRILIST (0x0<<18) -#define PRIM3D_TRISTRIP (0x1<<18) -#define PRIM3D_TRISTRIP_RVRSE (0x2<<18) -#define PRIM3D_TRIFAN (0x3<<18) -#define PRIM3D_POLY (0x4<<18) -#define PRIM3D_LINELIST (0x5<<18) -#define PRIM3D_LINESTRIP (0x6<<18) -#define PRIM3D_RECTLIST (0x7<<18) -#define PRIM3D_POINTLIST (0x8<<18) -#define PRIM3D_DIB (0x9<<18) -#define PRIM3D_MASK (0x1f<<18) - -#define I915PACKCOLOR4444(r,g,b,a) \ - ((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4)) - -#define I915PACKCOLOR1555(r,g,b,a) \ - ((((r) & 0xf8) << 7) | (((g) & 0xf8) << 2) | (((b) & 0xf8) >> 3) | \ - ((a) ? 0x8000 : 0)) - -#define I915PACKCOLOR565(r,g,b) \ - ((((r) & 0xf8) << 8) | (((g) & 0xfc) << 3) | (((b) & 0xf8) >> 3)) - -#define I915PACKCOLOR8888(r,g,b,a) \ - ((a<<24) | (r<<16) | (g<<8) | b) - - - - -#define BR00_BITBLT_CLIENT 0x40000000 -#define BR00_OP_COLOR_BLT 0x10000000 -#define BR00_OP_SRC_COPY_BLT 0x10C00000 -#define BR13_SOLID_PATTERN 0x80000000 - -#define XY_SETUP_BLT_CMD (CMD_2D | (1 << 22) | 6) - -#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) -#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) -#define XY_COLOR_BLT_WRITE_RGB (1<<20) - -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) - -#define XY_BLT_WRITE_ALPHA (1<<21) -#define XY_BLT_WRITE_RGB (1<<20) -#define XY_SRC_TILED (1<<15) -#define XY_DST_TILED (1<<11) - -#define FENCE_LINEAR 0 -#define FENCE_XMAJOR 1 -#define FENCE_YMAJOR 2 - -#endif diff --git a/src/mesa/drivers/dri/i915/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h similarity index 65% rename from src/mesa/drivers/dri/i915/intel_reg.h rename to src/mesa/drivers/dri/intel/intel_reg.h index 7828ba6ad39..b9bbcdc704d 100644 --- a/src/mesa/drivers/dri/i915/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -25,16 +25,19 @@ * **************************************************************************/ +#define CMD_MI (0x0 << 29) +#define CMD_2D (0x2 << 29) +#define CMD_3D (0x3 << 29) -#ifndef _INTEL_REG_H_ -#define _INTEL_REG_H_ - - - -#define CMD_3D (0x3<<29) +#define MI_BATCH_BUFFER_END (CMD_MI | 0xA << 23) +/* Stalls command execution waiting for the given events to have occurred. */ +#define MI_WAIT_FOR_EVENT (CMD_MI | (0x3 << 23)) +#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) +#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) -#define _3DPRIMITIVE ((0x3<<29)|(0x1f<<24)) +/* Primitive dispatch on 830-945 */ +#define _3DPRIMITIVE (CMD_3D | (0x1f << 24)) #define PRIM_INDIRECT (1<<23) #define PRIM_INLINE (0<<23) #define PRIM_INDIRECT_SEQUENTIAL (0<<17) @@ -52,37 +55,22 @@ #define PRIM3D_DIB (0x9<<18) #define PRIM3D_MASK (0x1f<<18) -#define I915PACKCOLOR4444(r,g,b,a) \ - ((((a) & 0xf0) << 8) | (((r) & 0xf0) << 4) | ((g) & 0xf0) | ((b) >> 4)) - -#define I915PACKCOLOR1555(r,g,b,a) \ - ((((r) & 0xf8) << 7) | (((g) & 0xf8) << 2) | (((b) & 0xf8) >> 3) | \ - ((a) ? 0x8000 : 0)) - -#define I915PACKCOLOR565(r,g,b) \ - ((((r) & 0xf8) << 8) | (((g) & 0xfc) << 3) | (((b) & 0xf8) >> 3)) +#define XY_SETUP_BLT_CMD (CMD_2D | (0x011 << 22) | 6) -#define I915PACKCOLOR8888(r,g,b,a) \ - ((a<<24) | (r<<16) | (g<<8) | b) +#define XY_COLOR_BLT_CMD (CMD_2D | (0x50 << 22) | 4) +#define XY_SRC_COPY_BLT_CMD (CMD_2D | (0x53 << 22) | 6) +/* BR00 */ +#define XY_BLT_WRITE_ALPHA (1 << 21) +#define XY_BLT_WRITE_RGB (1 << 20) +#define XY_SRC_TILED (1 << 15) +#define XY_DST_TILED (1 << 11) +/* BR13 */ +#define BR13_565 (0x1 << 24) +#define BR13_8888 (0x3 << 24) -#define BR00_BITBLT_CLIENT 0x40000000 -#define BR00_OP_COLOR_BLT 0x10000000 -#define BR00_OP_SRC_COPY_BLT 0x10C00000 -#define BR13_SOLID_PATTERN 0x80000000 - -#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|0x4) -#define XY_COLOR_BLT_WRITE_ALPHA (1<<21) -#define XY_COLOR_BLT_WRITE_RGB (1<<20) - -#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) -#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) -#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) - -#define MI_WAIT_FOR_EVENT ((0x3<<23)) -#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) -#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) - -#endif +#define FENCE_LINEAR 0 +#define FENCE_XMAJOR 1 +#define FENCE_YMAJOR 2 -- 2.30.2