From 6bc40f9af5b35724caff9fa7ced47b2ca6183f22 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 28 Oct 2013 16:06:10 -0700 Subject: [PATCH] i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum. Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more obvious than passing true or false. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 +- src/mesa/drivers/dri/i965/brw_context.h | 7 ++++++- src/mesa/drivers/dri/i965/brw_draw.c | 2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++++++------- src/mesa/drivers/dri/i965/intel_batchbuffer.h | 20 ++++++++++--------- src/mesa/drivers/dri/i965/intel_blit.c | 6 +++--- 6 files changed, 29 insertions(+), 23 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 4cbcebe5b32..e555f465656 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -210,7 +210,7 @@ brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params) intel_batchbuffer_emit_mi_flush(brw); retry: - intel_batchbuffer_require_space(brw, estimated_max_batch_usage, false); + intel_batchbuffer_require_space(brw, estimated_max_batch_usage, RENDER_RING); intel_batchbuffer_save_state(brw); drm_intel_bo *saved_bo = brw->batch.bo; uint32_t saved_used = brw->batch.used; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 4a089868339..7576a22c955 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -861,6 +861,11 @@ struct intel_sync_object { drm_intel_bo *bo; }; +enum brw_gpu_ring { + RENDER_RING, + BLT_RING, +}; + struct intel_batchbuffer { /** Current batchbuffer being queued up. */ drm_intel_bo *bo; @@ -879,7 +884,7 @@ struct intel_batchbuffer { #define BATCH_SZ (8192*sizeof(uint32_t)) uint32_t state_batch_offset; - bool is_blit; + enum brw_gpu_ring ring; bool needs_sol_reset; struct { diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 7b33b76e75a..1da45df4aba 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -392,7 +392,7 @@ static bool brw_try_draw_prims( struct gl_context *ctx, * we've got validated state that needs to be in the same batch as the * primitives. */ - intel_batchbuffer_require_space(brw, estimated_max_prim_size, false); + intel_batchbuffer_require_space(brw, estimated_max_prim_size, RENDER_RING); intel_batchbuffer_save_state(brw); if (brw->num_instances != prims[i].num_instances) { diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index babe9ea1ad9..672bc021486 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -260,19 +260,18 @@ do_flush_locked(struct brw_context *brw) if (!brw->intelScreen->no_hw) { int flags; - if (brw->gen < 6 || !batch->is_blit) { - flags = I915_EXEC_RENDER; + if (brw->gen >= 6 && batch->ring == BLT_RING) { + flags = I915_EXEC_BLT; } else { - flags = I915_EXEC_BLT; + flags = I915_EXEC_RENDER; } - if (batch->needs_sol_reset) flags |= I915_EXEC_GEN7_SOL_RESET; if (ret == 0) { if (unlikely(INTEL_DEBUG & DEBUG_AUB)) brw_annotate_aub(brw); - if (brw->hw_ctx == NULL || batch->is_blit) { + if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) { ret = drm_intel_bo_mrb_exec(batch->bo, 4 * batch->used, NULL, 0, 0, flags); } else { @@ -401,10 +400,10 @@ intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw, void intel_batchbuffer_data(struct brw_context *brw, - const void *data, GLuint bytes, bool is_blit) + const void *data, GLuint bytes, enum brw_gpu_ring ring) { assert((bytes & 3) == 0); - intel_batchbuffer_require_space(brw, bytes, is_blit); + intel_batchbuffer_require_space(brw, bytes, ring); __memcpy(brw->batch.map + brw->batch.used, data, bytes); brw->batch.used += bytes >> 2; } @@ -613,7 +612,7 @@ void intel_batchbuffer_emit_mi_flush(struct brw_context *brw) { if (brw->gen >= 6) { - if (brw->batch.is_blit) { + if (brw->batch.ring == BLT_RING) { BEGIN_BATCH_BLT(4); OUT_BATCH(MI_FLUSH_DW); OUT_BATCH(0); diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index cabbb69a63c..40b0a296a96 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -43,7 +43,8 @@ int _intel_batchbuffer_flush(struct brw_context *brw, * intel_buffer_dword() calls. */ void intel_batchbuffer_data(struct brw_context *brw, - const void *data, GLuint bytes, bool is_blit); + const void *data, GLuint bytes, + enum brw_gpu_ring ring); bool intel_batchbuffer_emit_reloc(struct brw_context *brw, drm_intel_bo *buffer, @@ -101,14 +102,15 @@ intel_batchbuffer_emit_float(struct brw_context *brw, float f) } static INLINE void -intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz, int is_blit) +intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz, + enum brw_gpu_ring ring) { - if (brw->gen >= 6 && - brw->batch.is_blit != is_blit && brw->batch.used) { + /* If we're switching rings, implicitly flush the batch. */ + if (unlikely(ring != brw->batch.ring) && brw->batch.used && brw->gen >= 6) { intel_batchbuffer_flush(brw); } - brw->batch.is_blit = is_blit; + brw->batch.ring = ring; #ifdef DEBUG assert(sz < BATCH_SZ - BATCH_RESERVED); @@ -118,9 +120,9 @@ intel_batchbuffer_require_space(struct brw_context *brw, GLuint sz, int is_blit) } static INLINE void -intel_batchbuffer_begin(struct brw_context *brw, int n, bool is_blit) +intel_batchbuffer_begin(struct brw_context *brw, int n, enum brw_gpu_ring ring) { - intel_batchbuffer_require_space(brw, n * 4, is_blit); + intel_batchbuffer_require_space(brw, n * 4, ring); brw->batch.emit = brw->batch.used; #ifdef DEBUG @@ -146,8 +148,8 @@ intel_batchbuffer_advance(struct brw_context *brw) void intel_batchbuffer_cached_advance(struct brw_context *brw); -#define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, false) -#define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, true) +#define BEGIN_BATCH(n) intel_batchbuffer_begin(brw, n, RENDER_RING) +#define BEGIN_BATCH_BLT(n) intel_batchbuffer_begin(brw, n, BLT_RING) #define OUT_BATCH(d) intel_batchbuffer_emit_dword(brw, d) #define OUT_BATCH_F(f) intel_batchbuffer_emit_float(brw, f) #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 0a03859df3e..a47d02e8220 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -312,7 +312,7 @@ intelEmitCopyBlit(struct brw_context *brw, if (pass >= 2) return false; - intel_batchbuffer_require_space(brw, 8 * 4, true); + intel_batchbuffer_require_space(brw, 8 * 4, BLT_RING); DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", __FUNCTION__, src_buffer, src_pitch, src_offset, src_x, src_y, @@ -427,7 +427,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); - intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, true); + intel_batchbuffer_require_space(brw, (8 * 4) + (3 * 4) + dwords * 4, BLT_RING); opcode = XY_SETUP_BLT_CMD; if (cpp == 4) @@ -461,7 +461,7 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw, OUT_BATCH(((y + h) << 16) | (x + w)); ADVANCE_BATCH(); - intel_batchbuffer_data(brw, src_bits, dwords * 4, true); + intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING); intel_batchbuffer_emit_mi_flush(brw); -- 2.30.2