From 6be2bef81f91cd6fe7fc1f1e7b21a6764055d192 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Sun, 30 Jun 2019 23:12:07 +0200 Subject: [PATCH] sse.md (ssse3_abs2): Rename from abs2. * config/i386/sse.md (ssse3_abs2): Rename from abs2. (abs2): New expander. * config/i386/i386-builtin.def (__builtin_ia32_pabsb): Use CODE_FOR_ssse3_absv8qi2. (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2. (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2. From-SVN: r272835 --- gcc/ChangeLog | 9 +++++++++ gcc/config/i386/i386-builtin.def | 6 +++--- gcc/config/i386/sse.md | 8 +++++++- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 879aa2eac7d..e41c135c43f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2019-06-30 Uroš Bizjak + + * config/i386/sse.md (ssse3_abs2): Rename from abs2. + (abs2): New expander. + * config/i386/i386-builtin.def (__builtin_ia32_pabsb): + Use CODE_FOR_ssse3_absv8qi2. + (__builtin_ia32_pabsw): Use CODE_FOR_ssse3_absv4hi2. + (__builtin_ia32_pabsd): Use CODE_FOR_ssse3_absv2si2. + 2019-06-30 Uroš Bizjak * config/i386/i386.md (mmx_isa): Rename x64, x64_noavx and x64_avx diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index aad62f3e401..ef453114aac 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -830,11 +830,11 @@ BDESC (OPTION_MASK_ISA_SSE3, 0, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd" /* SSSE3 */ BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI) -BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) +BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI) BDESC (OPTION_MASK_ISA_SSSE3, 0, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI) BDESC (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_MMX, 0, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index e46a83e7014..0494cbf08ac 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16584,7 +16584,7 @@ } }) -(define_insn "abs2" +(define_insn "ssse3_abs2" [(set (match_operand:MMXMODEI 0 "register_operand" "=y,Yv") (abs:MMXMODEI (match_operand:MMXMODEI 1 "register_mmxmem_operand" "ym,Yv")))] @@ -16599,6 +16599,12 @@ (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)")) (set_attr "mode" "DI,TI")]) +(define_insn "abs2" + [(set (match_operand:MMXMODEI 0 "register_operand") + (abs:MMXMODEI + (match_operand:MMXMODEI 1 "register_operand")))] + "TARGET_MMX_WITH_SSE && TARGET_SSSE3") + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; AMD SSE4A instructions -- 2.30.2