From 6be3e1a336617bda24308791f0907c5d61729027 Mon Sep 17 00:00:00 2001 From: Matt Johnston Date: Mon, 7 Feb 2022 17:09:20 +0800 Subject: [PATCH] valentyusb: Add USB UART to SOC and OrangeCrab An extra uart is added at 0xc0008000 attached to valentyusb, using the OrangeCrab's onboard USB port. This has a liteuart interface, an identifier bit is added to syscon. Generated from branch hw_cdc_eptri of https://github.com/litex-hub/valentyusb The generate script is based on valentyusb/sim/generate_verilog.py UARTUSB: usbserial@8000 { device_type = "serial"; compatible = "litex,liteuart"; reg = <0x8000 0x100>; interrupts = <0x15 0x1>; }; (requires extra kernel patches for early console at present v5.16) Signed-off-by: Matt Johnston --- Makefile | 1 + fpga/top-orangecrab0.2.vhdl | 12 + include/microwatt_soc.h | 7 +- soc.vhdl | 105 +- syscon.vhdl | 7 +- valentyusb/gen-src/generate.py | 263 ++ valentyusb/gen-src/generate.sh | 15 + valentyusb/gen-src/orangecrab-85-0.2.yml | 7 + .../gateware/build_valentyusb.sh | 5 + .../gateware/out_buffer.init | 249 ++ .../orangecrab-85-0.2/gateware/valentyusb.lpf | 118 + .../orangecrab-85-0.2/gateware/valentyusb.v | 3983 +++++++++++++++++ .../orangecrab-85-0.2/gateware/valentyusb.ys | 6 + .../software/include/generated/csr.h | 232 + .../software/include/generated/git.h | 9 + .../software/include/generated/mem.h | 15 + .../software/include/generated/soc.h | 40 + 17 files changed, 5068 insertions(+), 6 deletions(-) create mode 100755 valentyusb/gen-src/generate.py create mode 100755 valentyusb/gen-src/generate.sh create mode 100644 valentyusb/gen-src/orangecrab-85-0.2.yml create mode 100644 valentyusb/generated/orangecrab-85-0.2/gateware/build_valentyusb.sh create mode 100644 valentyusb/generated/orangecrab-85-0.2/gateware/out_buffer.init create mode 100644 valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.lpf create mode 100644 valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v create mode 100644 valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.ys create mode 100644 valentyusb/generated/orangecrab-85-0.2/software/include/generated/csr.h create mode 100644 valentyusb/generated/orangecrab-85-0.2/software/include/generated/git.h create mode 100644 valentyusb/generated/orangecrab-85-0.2/software/include/generated/mem.h create mode 100644 valentyusb/generated/orangecrab-85-0.2/software/include/generated/soc.h diff --git a/Makefile b/Makefile index dbe62ba..330ed48 100644 --- a/Makefile +++ b/Makefile @@ -192,6 +192,7 @@ ECP_FLASH_OFFSET=0x80000 toplevel=fpga/top-orangecrab0.2.vhdl litedram_target=orangecrab-85-0.2 soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v +soc_extra_v += valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v dmi_dtm=dmi_dtm_ecp5.vhdl endif diff --git a/fpga/top-orangecrab0.2.vhdl b/fpga/top-orangecrab0.2.vhdl index e3e9c80..8197f51 100644 --- a/fpga/top-orangecrab0.2.vhdl +++ b/fpga/top-orangecrab0.2.vhdl @@ -23,6 +23,7 @@ entity toplevel is LOG_LENGTH : natural := 0; UART_IS_16550 : boolean := true; HAS_UART1 : boolean := false; + HAS_UARTUSB : boolean := true; USE_LITESDCARD : boolean := true; ICACHE_NUM_LINES : natural := 64; NGPIO : natural := 0 @@ -35,6 +36,11 @@ entity toplevel is pin_gpio_0 : out std_ulogic; pin_gpio_1 : in std_ulogic; + -- USB signals: + usb_d_p : in std_ulogic; + usb_d_n : in std_ulogic; + usb_pullup : out std_ulogic; + -- LEDs led0_b : out std_ulogic; led0_g : out std_ulogic; @@ -186,6 +192,7 @@ begin LOG_LENGTH => LOG_LENGTH, UART0_IS_16550 => UART_IS_16550, HAS_UART1 => HAS_UART1, + HAS_UARTUSB => HAS_UARTUSB, HAS_SD_CARD => USE_LITESDCARD, ICACHE_NUM_LINES => ICACHE_NUM_LINES, HAS_SHORT_MULT => true, @@ -194,12 +201,17 @@ begin port map ( -- System signals system_clk => system_clk, + clk_48 => ext_clk, rst => soc_rst, -- UART signals uart0_txd => pin_gpio_0, uart0_rxd => pin_gpio_1, + usb_d_p => usb_d_p, + usb_d_n => usb_d_n, + usb_pullup => usb_pullup, + -- UART1 signals --uart1_txd => uart_pmod_tx, --uart1_rxd => uart_pmod_rx, diff --git a/include/microwatt_soc.h b/include/microwatt_soc.h index b138be1..632ef1e 100644 --- a/include/microwatt_soc.h +++ b/include/microwatt_soc.h @@ -10,10 +10,13 @@ #define BRAM_BASE 0x80000000 /* Internal BRAM */ #define SYSCON_BASE 0xc0000000 /* System control regs */ -#define UART_BASE 0xc0002000 /* UART */ +#define UART0_BASE 0xc0002000 /* UART */ +#define UART_BASE UART0_BASE +#define UART1_BASE 0xc0003000 /* UART */ #define XICS_ICP_BASE 0xc0004000 /* Interrupt controller */ #define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */ #define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */ +#define UARTUSB_BASE 0xc0008000 /* ValentyUSB UART */ #define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */ #define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */ #define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */ @@ -26,6 +29,7 @@ */ #define IRQ_UART0 0 #define IRQ_ETHERNET 1 +#define IRQ_UARTUSB 5 /* * Register definitions for the syscon registers @@ -42,6 +46,7 @@ #define SYS_REG_INFO_HAS_UART1 (1ull << 6) #define SYS_REG_INFO_HAS_ARTB (1ull << 7) #define SYS_REG_INFO_HAS_LITESDCARD (1ull << 8) +#define SYS_REG_INFO_HAS_UARTUSB (1ull << 9) #define SYS_REG_BRAMINFO 0x10 #define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull #define SYS_REG_DRAMINFO 0x18 diff --git a/soc.vhdl b/soc.vhdl index ee1ea3e..a65191c 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -25,6 +25,7 @@ use work.wishbone_types.all; -- 0xc0005000: XICS ICS -- 0xc0006000: SPI Flash controller -- 0xc0007000: GPIO controller +-- 0xc0008000: USB UART (valentyusb) -- 0xc8nnnnnn: External IO bus -- 0xf0000000: Flash "ROM" mapping -- 0xff000000: DRAM init code (if any) or flash ROM (**) @@ -50,6 +51,7 @@ use work.wishbone_types.all; -- 2 : UART1 -- 3 : SD card -- 4 : GPIO +-- 5 : UARTUSB entity soc is generic ( @@ -74,6 +76,7 @@ entity soc is HAS_LITEETH : boolean := false; UART0_IS_16550 : boolean := true; HAS_UART1 : boolean := false; + HAS_UARTUSB : boolean := false; ICACHE_NUM_LINES : natural := 64; ICACHE_NUM_WAYS : natural := 2; ICACHE_TLB_SIZE : natural := 64; @@ -88,6 +91,7 @@ entity soc is port( rst : in std_ulogic; system_clk : in std_ulogic; + clk_48 : in std_ulogic := '0'; -- "Large" (64-bit) DRAM wishbone wb_dram_in : out wishbone_master_out; @@ -117,6 +121,11 @@ entity soc is uart1_txd : out std_ulogic; uart1_rxd : in std_ulogic := '0'; + -- USB signals: + usb_d_p : in std_ulogic := '0'; + usb_d_n : in std_ulogic := '0'; + usb_pullup : out std_ulogic; + -- SPI Flash signals spi_flash_sck : out std_ulogic; spi_flash_cs_n : out std_ulogic; @@ -181,6 +190,11 @@ architecture behaviour of soc is signal uart1_dat8 : std_ulogic_vector(7 downto 0); signal uart1_irq : std_ulogic; + -- UARTUSB signals: + signal wb_uartusb_in : wb_io_master_out; + signal wb_uartusb_out : wb_io_slave_out; + signal uartusb_irq : std_ulogic; + -- SPI Flash controller signals: signal wb_spiflash_in : wb_io_master_out; signal wb_spiflash_out : wb_io_slave_out; @@ -241,6 +255,7 @@ architecture behaviour of soc is SLAVE_IO_UART1, SLAVE_IO_SPI_FLASH, SLAVE_IO_GPIO, + SLAVE_IO_UARTUSB, SLAVE_IO_EXTERNAL); signal current_io_decode : slave_io_type; @@ -248,6 +263,7 @@ architecture behaviour of soc is signal io_cycle_syscon : std_ulogic; signal io_cycle_uart : std_ulogic; signal io_cycle_uart1 : std_ulogic; + signal io_cycle_uartusb : std_ulogic; signal io_cycle_icp : std_ulogic; signal io_cycle_ics : std_ulogic; signal io_cycle_spi_flash : std_ulogic; @@ -310,6 +326,7 @@ architecture behaviour of soc is ); end component; + constant UART0_IS_POTATO : boolean := not UART0_IS_16550; begin resets: process(system_clk) @@ -609,6 +626,7 @@ begin io_cycle_syscon <= '0'; io_cycle_uart <= '0'; io_cycle_uart1 <= '0'; + io_cycle_uartusb <= '0'; io_cycle_icp <= '0'; io_cycle_ics <= '0'; io_cycle_spi_flash <= '0'; @@ -675,6 +693,9 @@ begin elsif std_match(match, x"C0007") then slave_io := SLAVE_IO_GPIO; io_cycle_gpio <= '1'; + elsif std_match(match, x"C0008") then + slave_io := SLAVE_IO_UARTUSB; + io_cycle_uartusb <= '1'; else io_cycle_none <= '1'; end if; @@ -702,6 +723,12 @@ begin wb_gpio_in <= wb_sio_out; wb_gpio_in.cyc <= io_cycle_gpio; + wb_uartusb_in <= wb_sio_out; + wb_uartusb_in.cyc <= io_cycle_uartusb; + -- valentyusb was built at base 0x0, it only needs 5 low bits + wb_uartusb_in.adr <= (others => '0'); + wb_uartusb_in.adr(4 downto 0) <= wb_sio_out.adr(4 downto 0); + -- Only give xics 8 bits of wb addr (for now...) wb_xics_icp_in <= wb_sio_out; wb_xics_icp_in.adr <= (others => '0'); @@ -731,6 +758,8 @@ begin wb_sio_in <= wb_xics_ics_out; when SLAVE_IO_UART1 => wb_sio_in <= wb_uart1_out; + when SLAVE_IO_UARTUSB => + wb_sio_in <= wb_uartusb_out; when SLAVE_IO_SPI_FLASH => wb_sio_in <= wb_spiflash_out; when SLAVE_IO_GPIO => @@ -760,7 +789,8 @@ begin HAS_LITEETH => HAS_LITEETH, HAS_SD_CARD => HAS_SD_CARD, UART0_IS_16550 => UART0_IS_16550, - HAS_UART1 => HAS_UART1 + HAS_UART1 => HAS_UART1, + HAS_UARTUSB => HAS_UARTUSB ) port map( clk => system_clk, @@ -777,7 +807,7 @@ begin -- -- Either potato (legacy) or 16550 -- - uart0_pp: if not UART0_IS_16550 generate + uart0_pp: if UART0_IS_POTATO generate uart0: entity work.pp_soc_uart generic map( FIFO_DEPTH => 32 @@ -796,6 +826,9 @@ begin wb_we_in => wb_uart0_in.we, wb_ack_out => wb_uart0_out.ack ); + + wb_uart0_out.dat <= x"000000" & uart0_dat8; + wb_uart0_out.stall <= not wb_uart0_out.ack; end generate; uart0_16550 : if UART0_IS_16550 generate @@ -830,10 +863,73 @@ begin uart0_irq <= irq_l; end if; end process; + + wb_uart0_out.dat <= x"000000" & uart0_dat8; + wb_uart0_out.stall <= not wb_uart0_out.ack; end generate; - wb_uart0_out.dat <= x"000000" & uart0_dat8; - wb_uart0_out.stall <= not wb_uart0_out.ack; + + uart0_valentyusb : if HAS_UARTUSB generate + component valentyusb port ( + clk_clksys : in std_ulogic; + clk_clk48 : in std_ulogic; + reset : in std_ulogic; + usb_d_p : in std_ulogic; + usb_d_n : in std_ulogic; + usb_pullup : out std_ulogic; + usb_tx_en : out std_ulogic; + interrupt : out std_ulogic; + wishbone_adr : in std_ulogic_vector(29 downto 0); + wishbone_dat_w : in std_ulogic_vector(31 downto 0); + wishbone_dat_r : out std_ulogic_vector(31 downto 0); + wishbone_sel : in std_ulogic_vector(3 downto 0); + wishbone_cyc : in std_ulogic; + wishbone_stb : in std_ulogic; + wishbone_ack : out std_ulogic; + wishbone_we : in std_ulogic; + wishbone_cti : in std_ulogic_vector(2 downto 0); + wishbone_bte : in std_ulogic_vector(1 downto 0); + wishbone_err : out std_ulogic + ); + end component; + signal irq_l : std_ulogic; + begin + uart0: valentyusb + port map ( + clk_clksys => system_clk, + clk_clk48 => clk_48, + reset => rst_uart, + usb_d_p => usb_d_p, + usb_d_n => usb_d_n, + usb_pullup => usb_pullup, + -- TODO, output flag + usb_tx_en => open, + wishbone_adr => "0000000000000000" & wb_uartusb_in.adr(13 downto 0), + wishbone_dat_r => wb_uartusb_out.dat, + wishbone_dat_w => wb_uartusb_in.dat, + wishbone_sel => wb_uartusb_in.sel, + wishbone_cyc => wb_uartusb_in.cyc, + wishbone_stb => wb_uartusb_in.stb, + wishbone_ack => wb_uartusb_out.ack, + wishbone_we => wb_uartusb_in.we, + interrupt => irq_l, + -- XXX matt check this + wishbone_cti => "000", + -- XXX matt check this + wishbone_bte => "00", + wishbone_err => open + ); + + wb_uartusb_out.stall <= not wb_uartusb_out.ack; + + -- Add a register on the irq out, helps timing + uartusb_irq_latch: process(system_clk) + begin + if rising_edge(system_clk) then + uartusb_irq <= irq_l; + end if; + end process; + end generate; -- -- UART1 @@ -961,6 +1057,7 @@ begin int_level_in(2) <= uart1_irq; int_level_in(3) <= ext_irq_sdcard; int_level_in(4) <= gpio_intr; + int_level_in(5) <= uartusb_irq; end process; -- BRAM Memory slave diff --git a/syscon.vhdl b/syscon.vhdl index 5e6cb00..97a4277 100644 --- a/syscon.vhdl +++ b/syscon.vhdl @@ -20,7 +20,8 @@ entity syscon is HAS_LITEETH : boolean; HAS_SD_CARD : boolean; UART0_IS_16550 : boolean; - HAS_UART1 : boolean + HAS_UART1 : boolean; + HAS_UARTUSB : boolean := false ); port ( clk : in std_ulogic; @@ -67,6 +68,7 @@ architecture behaviour of syscon is constant SYS_REG_INFO_HAS_URT1 : integer := 6; -- Has second UART constant SYS_REG_INFO_HAS_ARTB : integer := 7; -- Has architected TB frequency constant SYS_REG_INFO_HAS_SDCARD : integer := 8; -- Has LiteSDCard SD-card interface + constant SYS_REG_INFO_HAS_URTU : integer := 9; -- Has USB UART -- BRAMINFO contains the BRAM size in the bottom 52 bits -- DRAMINFO contains the DRAM size if any in the bottom 52 bits @@ -111,6 +113,7 @@ architecture behaviour of syscon is signal info_has_leth : std_ulogic; signal info_has_lsdc : std_ulogic; signal info_has_urt1 : std_ulogic; + signal info_has_urtu : std_ulogic; signal info_clk : std_ulogic_vector(39 downto 0); signal info_fl_off : std_ulogic_vector(31 downto 0); signal uinfo_16550 : std_ulogic; @@ -133,6 +136,7 @@ begin info_has_leth <= '1' when HAS_LITEETH else '0'; info_has_lsdc <= '1' when HAS_SD_CARD else '0'; info_has_urt1 <= '1' when HAS_UART1 else '0'; + info_has_urtu <= '1' when HAS_UARTUSB else '0'; info_clk <= std_ulogic_vector(to_unsigned(CLK_FREQ, 40)); reg_info <= (SYS_REG_INFO_HAS_UART => info_has_uart, SYS_REG_INFO_HAS_DRAM => info_has_dram, @@ -142,6 +146,7 @@ begin SYS_REG_INFO_HAS_SDCARD => info_has_lsdc, SYS_REG_INFO_HAS_LSYS => '1', SYS_REG_INFO_HAS_URT1 => info_has_urt1, + SYS_REG_INFO_HAS_URTU => info_has_urtu, others => '0'); reg_braminfo <= x"000" & std_ulogic_vector(to_unsigned(BRAM_SIZE, 52)); diff --git a/valentyusb/gen-src/generate.py b/valentyusb/gen-src/generate.py new file mode 100755 index 0000000..4732b60 --- /dev/null +++ b/valentyusb/gen-src/generate.py @@ -0,0 +1,263 @@ +#!/usr/bin/env python3 + +# Based on valentyusb/sim/generate_verilog.py , modified +# for Microwatt + +# This variable defines all the external programs that this module +# relies on. lxbuildenv reads this variable in order to ensure +# the build will finish without exiting due to missing third-party +# programs. +LX_DEPENDENCIES = [] + +# Import lxbuildenv to integrate the deps/ directory +#import lxbuildenv + +# Disable pylint's E1101, which breaks completely on migen +#pylint:disable=E1101 + +import argparse +import os +import yaml + +#from migen import * +from migen import Module, Signal, Instance, ClockDomain, If +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.fhdl.specials import TSTriple +from migen.fhdl.bitcontainer import bits_for +from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat + +# from litex.build.sim.platform import SimPlatform +from litex.build.lattice import LatticePlatform +from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal +from litex.soc.integration.soc_core import SoCCore +from litex.soc.integration.builder import Builder +from litex.soc.interconnect import wishbone +from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage + +from valentyusb import usbcore +from valentyusb.usbcore import io as usbio +from valentyusb.usbcore.cpu import dummyusb, cdc_eptri, eptri, epfifo +from valentyusb.usbcore.endpoint import EndpointType + +_connectors = [] + +class _CRG(Module): + def __init__(self, platform): + clk = platform.request("clk") + rst = platform.request("reset") + + clk12 = Signal() + + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + self.clock_domains.cd_usb_48_to_12 = ClockDomain() + + clk48 = clk.clk48 + + self.comb += self.cd_usb_48.clk.eq(clk48) + self.comb += self.cd_usb_48_to_12.clk.eq(clk48) + + clk12_counter = Signal(2) + self.sync.usb_48_to_12 += clk12_counter.eq(clk12_counter + 1) + + self.comb += clk12.eq(clk12_counter[1]) + + self.comb += self.cd_sys.clk.eq(clk.clksys) + self.comb += self.cd_usb_12.clk.eq(clk12) + + self.comb += [ + ResetSignal("sys").eq(rst), + ResetSignal("usb_12").eq(rst), + ResetSignal("usb_48").eq(rst), + ] + +class BaseSoC(SoCCore): + + def __init__(self, platform, io, sys_freq, output_dir="build", usb_variant='dummy', **kwargs): + # Disable integrated RAM as we'll add it later + self.integrated_sram_size = 0 + + self.output_dir = output_dir + + platform.add_extension(io) + + self.submodules.crg = _CRG(platform) + + # prior to SocCore.__init__ + self.csr_map = { + "uart": 0, # microwatt soc will remap addresses to 0 + } + + SoCCore.__init__(self, platform, sys_freq, + cpu_type=None, + integrated_rom_size=0x0, + integrated_sram_size=0x0, + integrated_main_ram_size=0x0, + csr_address_width=14, csr_data_width=32, + with_uart=False, with_timer=False) + + # Add USB pads + usb_pads = platform.request("usb") + usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup) + self.comb += usb_pads.tx_en.eq(usb_iobuf.usb_tx_en) + if usb_variant == 'eptri': + self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=True) + elif usb_variant == 'epfifo': + self.submodules.usb = epfifo.PerEndpointFifoInterface(usb_iobuf, debug=True) + elif usb_variant == 'cdc_eptri': + extra_args = {} + passthrough = ['product', 'manufacturer'] + for p in passthrough: + try: + extra_args[p] = kwargs[p] + except KeyError: + pass + self.submodules.uart = cdc_eptri.CDCUsb(usb_iobuf, debug=True, **extra_args) + elif usb_variant == 'dummy': + self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True) + else: + raise ValueError('Invalid endpoints value. It is currently \'eptri\' and \'dummy\'') + try: + self.add_wb_master(self.usb.debug_bridge.wishbone) + except AttributeError: + pass + + if self.uart: + self.comb += self.platform.request("interrupt").eq(self.uart.ev.irq) + + wb_ctrl = wishbone.Interface() + self.add_wb_master(wb_ctrl) + platform.add_extension(wb_ctrl.get_ios("wb_ctrl")) + self.comb += wb_ctrl.connect_to_pads(self.platform.request("wishbone"), mode="slave") + +def add_fsm_state_names(): + """Hack the FSM module to add state names to the output""" + from migen.fhdl.visit import NodeTransformer + from migen.genlib.fsm import NextState, NextValue, _target_eq + from migen.fhdl.bitcontainer import value_bits_sign + + class My_LowerNext(NodeTransformer): + def __init__(self, next_state_signal, next_state_name_signal, encoding, aliases): + self.next_state_signal = next_state_signal + self.next_state_name_signal = next_state_name_signal + self.encoding = encoding + self.aliases = aliases + # (target, next_value_ce, next_value) + self.registers = [] + + def _get_register_control(self, target): + for x in self.registers: + if _target_eq(target, x[0]): + return x[1], x[2] + raise KeyError + + def visit_unknown(self, node): + if isinstance(node, NextState): + try: + actual_state = self.aliases[node.state] + except KeyError: + actual_state = node.state + return [ + self.next_state_signal.eq(self.encoding[actual_state]), + self.next_state_name_signal.eq(int.from_bytes(actual_state.encode(), byteorder="big")) + ] + elif isinstance(node, NextValue): + try: + next_value_ce, next_value = self._get_register_control(node.target) + except KeyError: + related = node.target if isinstance(node.target, Signal) else None + next_value = Signal(bits_sign=value_bits_sign(node.target), related=related) + next_value_ce = Signal(related=related) + self.registers.append((node.target, next_value_ce, next_value)) + return next_value.eq(node.value), next_value_ce.eq(1) + else: + return node + import migen.genlib.fsm as fsm + def my_lower_controls(self): + self.state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big")) + self.next_state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big")) + self.comb += self.next_state_name.eq(self.state_name) + self.sync += self.state_name.eq(self.next_state_name) + return My_LowerNext(self.next_state, self.next_state_name, self.encoding, self.state_aliases) + fsm.FSM._lower_controls = my_lower_controls + + +_io = [ + # Wishbone + ("wishbone", 0, + Subsignal("adr", Pins(30)), + Subsignal("dat_r", Pins(32)), + Subsignal("dat_w", Pins(32)), + Subsignal("sel", Pins(4)), + Subsignal("cyc", Pins(1)), + Subsignal("stb", Pins(1)), + Subsignal("ack", Pins(1)), + Subsignal("we", Pins(1)), + Subsignal("cti", Pins(3)), + Subsignal("bte", Pins(2)), + Subsignal("err", Pins(1)) + ), + ("usb", 0, + Subsignal("d_p", Pins(1)), + Subsignal("d_n", Pins(1)), + Subsignal("pullup", Pins(1)), + Subsignal("tx_en", Pins(1)), + ), + ("clk", 0, + Subsignal("clk48", Pins(1)), + Subsignal("clksys", Pins(1)), + ), + ("interrupt", 0, Pins(1)), + ("reset", 0, Pins(1)), +] + +def generate(core_config, output_dir, csr_csv): + + toolchain = core_config["toolchain"] + if toolchain == "trellis": + platform = LatticePlatform(core_config["device"], [], toolchain=toolchain) + else: + raise ValueError(f"Unknown config toolchain {toolchain}") + + soc = BaseSoC(platform, _io, core_config["sys_freq"], + usb_variant=core_config["usb_variant"], + cpu_type=None, cpu_variant=None, + output_dir=output_dir, + product=core_config["product"], + manufacturer="Microwatt") + builder = Builder(soc, output_dir=output_dir, + csr_csv=csr_csv, + compile_software=False) + vns = builder.build(run=False, build_name='valentyusb') + soc.do_exit(vns) + +def main(): + parser = argparse.ArgumentParser(description="Build standalone ValentyUSB verilog output") + # parser.add_argument('variant', metavar='VARIANT', + # choices=['dummy', 'cdc_eptri', 'eptri', 'epfifo'], + # default='dummy', + # help='USB variant. Choices: [%(choices)s] (default: %(default)s)' ) + parser.add_argument('--dir', metavar='DIRECTORY', + default='build', + help='Output directory (default: %(default)s)' ) + parser.add_argument('--csr', metavar='CSR', + default='csr.csv', + help='csr file (default: %(default)s)') + parser.add_argument('config', type=argparse.FileType('r'), + help='Input platform config file') + args = parser.parse_args() + + core_config = yaml.load(args.config.read(), Loader=yaml.Loader) + # XXX matt - not sure if this needed, maybe only for sim target? + # add_fsm_state_names() + output_dir = args.dir + generate(core_config, output_dir, args.csr) + + print( +"""Build complete. Output files: + {}/gateware/valentyusb.v Source Verilog file. +""".format(output_dir)) + +if __name__ == "__main__": + main() diff --git a/valentyusb/gen-src/generate.sh b/valentyusb/gen-src/generate.sh new file mode 100755 index 0000000..5fabd5e --- /dev/null +++ b/valentyusb/gen-src/generate.sh @@ -0,0 +1,15 @@ +#!/bin/sh + +# This requires https://github.com/litex-hub/valentyusb branch hw_cdc_eptri +# Tested with +# commit 912d8e6dc72d45e092e608ffcaabfeaaa6d4580f +# Date: Wed Jan 6 09:42:42 2021 +0100 + +set -e + +GENSRCDIR=$(dirname $0) +cd $GENSRCDIR + +for b in orangecrab-85-0.2; do + ./generate.py --dir ../generated/$b $b.yml +done diff --git a/valentyusb/gen-src/orangecrab-85-0.2.yml b/valentyusb/gen-src/orangecrab-85-0.2.yml new file mode 100644 index 0000000..08d4e2c --- /dev/null +++ b/valentyusb/gen-src/orangecrab-85-0.2.yml @@ -0,0 +1,7 @@ +{ + "device": "LFE5U-85F-8MG285C", + "toolchain": "trellis", + "usb_variant": "cdc_eptri", + "sys_freq": 48000000, + "product": "Microwatt on OrangeCrab", +} diff --git a/valentyusb/generated/orangecrab-85-0.2/gateware/build_valentyusb.sh b/valentyusb/generated/orangecrab-85-0.2/gateware/build_valentyusb.sh new file mode 100644 index 0000000..3daa627 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/gateware/build_valentyusb.sh @@ -0,0 +1,5 @@ +# Autogenerated by LiteX / git: -------- +set -e +yosys -l valentyusb.rpt valentyusb.ys +nextpnr-ecp5 --json valentyusb.json --lpf valentyusb.lpf --textcfg valentyusb.config --85k --package CSFBGA285 --speed 8 --timing-allow-fail --seed 1 +ecppack valentyusb.config --svf valentyusb.svf --bit valentyusb.bit --bootaddr 0 diff --git a/valentyusb/generated/orangecrab-85-0.2/gateware/out_buffer.init b/valentyusb/generated/orangecrab-85-0.2/gateware/out_buffer.init new file mode 100644 index 0000000..11e6a02 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/gateware/out_buffer.init @@ -0,0 +1,249 @@ +00 +09 +02 +3e +00 +02 +01 +00 +80 +32 +09 +04 +00 +00 +01 +02 +02 +00 +00 +05 +24 +00 +10 +01 +04 +24 +02 +02 +05 +24 +06 +00 +01 +07 +05 +81 +03 +08 +00 +40 +09 +04 +01 +00 +02 +0a +00 +00 +00 +07 +05 +02 +02 +40 +00 +00 +07 +05 +82 +02 +40 +00 +00 +12 +01 +00 +02 +02 +00 +00 +40 +09 +12 +f2 +5b +01 +01 +01 +02 +00 +01 +04 +03 +09 +04 +14 +03 +4d +00 +69 +00 +63 +00 +72 +00 +6f +00 +77 +00 +61 +00 +74 +00 +74 +00 +30 +03 +4d +00 +69 +00 +63 +00 +72 +00 +6f +00 +77 +00 +61 +00 +74 +00 +74 +00 +20 +00 +6f +00 +6e +00 +20 +00 +4f +00 +72 +00 +61 +00 +6e +00 +67 +00 +65 +00 +43 +00 +72 +00 +61 +00 +62 +00 +05 +0f +1d +00 +01 +18 +10 +05 +00 +38 +b6 +08 +34 +a9 +09 +a0 +47 +8b +fd +a0 +76 +88 +15 +b6 +65 +00 +01 +02 +01 +12 +03 +4d +53 +46 +54 +31 +30 +30 +7e +00 +00 +00 +00 +00 +00 +00 +00 +28 +00 +00 +00 +00 +01 +04 +00 +01 +00 +00 +00 +00 +00 +00 +00 +00 +01 +57 +49 +4e +55 +53 +42 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +00 +c2 +01 +00 +00 +00 +08 diff --git a/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.lpf b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.lpf new file mode 100644 index 0000000..1b628f1 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.lpf @@ -0,0 +1,118 @@ +BLOCK RESETPATHS; +BLOCK ASYNCPATHS; +LOCATE COMP "clk_clk48" SITE "X"; +LOCATE COMP "clk_clksys" SITE "X"; +LOCATE COMP "reset" SITE "X"; +LOCATE COMP "usb_d_p" SITE "X"; +LOCATE COMP "usb_d_n" SITE "X"; +LOCATE COMP "usb_pullup" SITE "X"; +LOCATE COMP "usb_tx_en" SITE "X"; +LOCATE COMP "interrupt" SITE "X"; +LOCATE COMP "wishbone_adr[0]" SITE "X"; +LOCATE COMP "wishbone_adr[1]" SITE "X"; +LOCATE COMP "wishbone_adr[2]" SITE "X"; +LOCATE COMP "wishbone_adr[3]" SITE "X"; +LOCATE COMP "wishbone_adr[4]" SITE "X"; +LOCATE COMP "wishbone_adr[5]" SITE "X"; +LOCATE COMP "wishbone_adr[6]" SITE "X"; +LOCATE COMP "wishbone_adr[7]" SITE "X"; +LOCATE COMP "wishbone_adr[8]" SITE "X"; +LOCATE COMP "wishbone_adr[9]" SITE "X"; +LOCATE COMP "wishbone_adr[10]" SITE "X"; +LOCATE COMP "wishbone_adr[11]" SITE "X"; +LOCATE COMP "wishbone_adr[12]" SITE "X"; +LOCATE COMP "wishbone_adr[13]" SITE "X"; +LOCATE COMP "wishbone_adr[14]" SITE "X"; +LOCATE COMP "wishbone_adr[15]" SITE "X"; +LOCATE COMP "wishbone_adr[16]" SITE "X"; +LOCATE COMP "wishbone_adr[17]" SITE "X"; +LOCATE COMP "wishbone_adr[18]" SITE "X"; +LOCATE COMP "wishbone_adr[19]" SITE "X"; +LOCATE COMP "wishbone_adr[20]" SITE "X"; +LOCATE COMP "wishbone_adr[21]" SITE "X"; +LOCATE COMP "wishbone_adr[22]" SITE "X"; +LOCATE COMP "wishbone_adr[23]" SITE "X"; +LOCATE COMP "wishbone_adr[24]" SITE "X"; +LOCATE COMP "wishbone_adr[25]" SITE "X"; +LOCATE COMP "wishbone_adr[26]" SITE "X"; +LOCATE COMP "wishbone_adr[27]" SITE "X"; +LOCATE COMP "wishbone_adr[28]" SITE "X"; +LOCATE COMP "wishbone_adr[29]" SITE "X"; +LOCATE COMP "wishbone_dat_r[0]" SITE "X"; +LOCATE COMP "wishbone_dat_r[1]" SITE "X"; +LOCATE COMP "wishbone_dat_r[2]" SITE "X"; +LOCATE COMP "wishbone_dat_r[3]" SITE "X"; +LOCATE COMP "wishbone_dat_r[4]" SITE "X"; +LOCATE COMP "wishbone_dat_r[5]" SITE "X"; +LOCATE COMP "wishbone_dat_r[6]" SITE "X"; +LOCATE COMP "wishbone_dat_r[7]" SITE "X"; +LOCATE COMP "wishbone_dat_r[8]" SITE "X"; +LOCATE COMP "wishbone_dat_r[9]" SITE "X"; +LOCATE COMP "wishbone_dat_r[10]" SITE "X"; +LOCATE COMP "wishbone_dat_r[11]" SITE "X"; +LOCATE COMP "wishbone_dat_r[12]" SITE "X"; +LOCATE COMP "wishbone_dat_r[13]" SITE "X"; +LOCATE COMP "wishbone_dat_r[14]" SITE "X"; +LOCATE COMP "wishbone_dat_r[15]" SITE "X"; +LOCATE COMP "wishbone_dat_r[16]" SITE "X"; +LOCATE COMP "wishbone_dat_r[17]" SITE "X"; +LOCATE COMP "wishbone_dat_r[18]" SITE "X"; +LOCATE COMP "wishbone_dat_r[19]" SITE "X"; +LOCATE COMP "wishbone_dat_r[20]" SITE "X"; +LOCATE COMP "wishbone_dat_r[21]" SITE "X"; +LOCATE COMP "wishbone_dat_r[22]" SITE "X"; +LOCATE COMP "wishbone_dat_r[23]" SITE "X"; +LOCATE COMP "wishbone_dat_r[24]" SITE "X"; +LOCATE COMP "wishbone_dat_r[25]" SITE "X"; +LOCATE COMP "wishbone_dat_r[26]" SITE "X"; +LOCATE COMP "wishbone_dat_r[27]" SITE "X"; +LOCATE COMP "wishbone_dat_r[28]" SITE "X"; +LOCATE COMP "wishbone_dat_r[29]" SITE "X"; +LOCATE COMP "wishbone_dat_r[30]" SITE "X"; +LOCATE COMP "wishbone_dat_r[31]" SITE "X"; +LOCATE COMP "wishbone_dat_w[0]" SITE "X"; +LOCATE COMP "wishbone_dat_w[1]" SITE "X"; +LOCATE COMP "wishbone_dat_w[2]" SITE "X"; +LOCATE COMP "wishbone_dat_w[3]" SITE "X"; +LOCATE COMP "wishbone_dat_w[4]" SITE "X"; +LOCATE COMP "wishbone_dat_w[5]" SITE "X"; +LOCATE COMP "wishbone_dat_w[6]" SITE "X"; +LOCATE COMP "wishbone_dat_w[7]" SITE "X"; +LOCATE COMP "wishbone_dat_w[8]" SITE "X"; +LOCATE COMP "wishbone_dat_w[9]" SITE "X"; +LOCATE COMP "wishbone_dat_w[10]" SITE "X"; +LOCATE COMP "wishbone_dat_w[11]" SITE "X"; +LOCATE COMP "wishbone_dat_w[12]" SITE "X"; +LOCATE COMP "wishbone_dat_w[13]" SITE "X"; +LOCATE COMP "wishbone_dat_w[14]" SITE "X"; +LOCATE COMP "wishbone_dat_w[15]" SITE "X"; +LOCATE COMP "wishbone_dat_w[16]" SITE "X"; +LOCATE COMP "wishbone_dat_w[17]" SITE "X"; +LOCATE COMP "wishbone_dat_w[18]" SITE "X"; +LOCATE COMP "wishbone_dat_w[19]" SITE "X"; +LOCATE COMP "wishbone_dat_w[20]" SITE "X"; +LOCATE COMP "wishbone_dat_w[21]" SITE "X"; +LOCATE COMP "wishbone_dat_w[22]" SITE "X"; +LOCATE COMP "wishbone_dat_w[23]" SITE "X"; +LOCATE COMP "wishbone_dat_w[24]" SITE "X"; +LOCATE COMP "wishbone_dat_w[25]" SITE "X"; +LOCATE COMP "wishbone_dat_w[26]" SITE "X"; +LOCATE COMP "wishbone_dat_w[27]" SITE "X"; +LOCATE COMP "wishbone_dat_w[28]" SITE "X"; +LOCATE COMP "wishbone_dat_w[29]" SITE "X"; +LOCATE COMP "wishbone_dat_w[30]" SITE "X"; +LOCATE COMP "wishbone_dat_w[31]" SITE "X"; +LOCATE COMP "wishbone_sel[0]" SITE "X"; +LOCATE COMP "wishbone_sel[1]" SITE "X"; +LOCATE COMP "wishbone_sel[2]" SITE "X"; +LOCATE COMP "wishbone_sel[3]" SITE "X"; +LOCATE COMP "wishbone_cyc" SITE "X"; +LOCATE COMP "wishbone_stb" SITE "X"; +LOCATE COMP "wishbone_ack" SITE "X"; +LOCATE COMP "wishbone_we" SITE "X"; +LOCATE COMP "wishbone_cti[0]" SITE "X"; +LOCATE COMP "wishbone_cti[1]" SITE "X"; +LOCATE COMP "wishbone_cti[2]" SITE "X"; +LOCATE COMP "wishbone_bte[0]" SITE "X"; +LOCATE COMP "wishbone_bte[1]" SITE "X"; +LOCATE COMP "wishbone_err" SITE "X"; \ No newline at end of file diff --git a/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v new file mode 100644 index 0000000..4c0ba6b --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v @@ -0,0 +1,3983 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : valentyusb.v +// Device : LFE5U-85F-8MG285C +// LiteX sha1 : -------- +// Date : 2022-02-07 17:23:11 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module valentyusb ( + input wire clk_clk48, + input wire clk_clksys, + input wire reset, + input wire usb_d_p, + input wire usb_d_n, + output wire usb_pullup, + output wire usb_tx_en, + output wire interrupt, + input wire [29:0] wishbone_adr, + output wire [31:0] wishbone_dat_r, + input wire [31:0] wishbone_dat_w, + input wire [3:0] wishbone_sel, + input wire wishbone_cyc, + input wire wishbone_stb, + output wire wishbone_ack, + input wire wishbone_we, + input wire [2:0] wishbone_cti, + input wire [1:0] wishbone_bte, + output wire wishbone_err +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire crg_clk12; +wire sys_clk; +wire sys_rst; +wire usb_12_clk; +wire usb_12_rst; +wire usb_48_clk; +wire usb_48_rst; +wire usb_48_to_12_clk; +reg usb_48_to_12_rst = 1'd0; +reg [1:0] crg_clk12_counter = 2'd0; +reg soc_rst = 1'd0; +wire cpu_rst; +reg [1:0] reset_storage = 2'd0; +reg reset_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg scratch_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg bus_errors_re = 1'd0; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +wire usb_iobuf_usb_tx_en; +wire usb_iobuf_usb_p_tx; +wire usb_iobuf_usb_n_tx; +reg usb_iobuf_usb_p_rx = 1'd0; +reg usb_iobuf_usb_n_rx = 1'd0; +wire usb_iobuf_usb_pullup; +wire usb_iobuf_usb_p_t_i; +wire usb_iobuf_usb_n_t_i; +wire cdcusbphy_usb_core_tx_i_bit_strobe; +reg [7:0] cdcusbphy_usb_core_tx_i_data_payload = 8'd0; +wire cdcusbphy_usb_core_tx_o_data_strobe; +reg cdcusbphy_usb_core_tx_i_oe = 1'd0; +wire cdcusbphy_usb_core_tx_o_usbp; +wire cdcusbphy_usb_core_tx_o_usbn; +wire cdcusbphy_usb_core_tx_o_oe; +wire [7:0] cdcusbphy_usb_core_tx_shifter_i_data; +reg cdcusbphy_usb_core_tx_shifter_o_get = 1'd0; +wire cdcusbphy_usb_core_tx_shifter_o_empty; +wire cdcusbphy_usb_core_tx_shifter_o_data; +reg [7:0] cdcusbphy_usb_core_tx_shifter_shifter = 8'd0; +reg [7:0] cdcusbphy_usb_core_tx_shifter_pos = 8'd1; +wire cdcusbphy_usb_core_tx_shifter_empty; +wire cdcusbphy_usb_core_tx_shifter_ce; +wire cdcusbphy_usb_core_tx_shifter_reset; +wire cdcusbphy_usb_core_tx_bitstuff_i_data; +wire cdcusbphy_usb_core_tx_bitstuff_o_stall; +reg cdcusbphy_usb_core_tx_bitstuff_o_will_stall = 1'd0; +reg cdcusbphy_usb_core_tx_bitstuff_o_data = 1'd0; +reg cdcusbphy_usb_core_tx_bitstuff_stuff_bit = 1'd0; +wire cdcusbphy_usb_core_tx_bitstuff_reset; +wire cdcusbphy_usb_core_tx_nrzi_i_valid; +wire cdcusbphy_usb_core_tx_nrzi_i_oe; +wire cdcusbphy_usb_core_tx_nrzi_i_data; +reg cdcusbphy_usb_core_tx_nrzi_usbp = 1'd0; +reg cdcusbphy_usb_core_tx_nrzi_usbn = 1'd0; +reg cdcusbphy_usb_core_tx_nrzi_oe0 = 1'd0; +reg cdcusbphy_usb_core_tx_nrzi_o_usbp = 1'd0; +reg cdcusbphy_usb_core_tx_nrzi_o_usbn = 1'd0; +reg cdcusbphy_usb_core_tx_nrzi_o_oe = 1'd0; +reg [7:0] cdcusbphy_usb_core_tx_sync_pulse = 8'd0; +wire cdcusbphy_usb_core_tx_fit_dat; +wire cdcusbphy_usb_core_tx_fit_oe; +reg cdcusbphy_usb_core_tx_da_reset_shifter = 1'd0; +reg cdcusbphy_usb_core_tx_da_reset_bitstuff = 1'd0; +wire cdcusbphy_usb_core_tx_stall; +wire cdcusbphy_usb_core_tx_sp_reset_bitstuff; +wire cdcusbphy_usb_core_tx_sp_reset_shifter; +wire cdcusbphy_usb_core_tx_sp_bit; +wire cdcusbphy_usb_core_tx_sp_o_data_strobe; +reg cdcusbphy_usb_core_tx_bitstuff_valid_data = 1'd0; +reg [1:0] cdcusbphy_usb_core_tx_state_gray = 2'd0; +wire cdcusbphy_usb_core_tx_state_data; +wire cdcusbphy_usb_core_tx_state_sync; +wire cdcusbphy_usb_core_tx_nrzi_dat; +wire cdcusbphy_usb_core_tx_nrzi_oe1; +reg cdcusbphy_usb_core_txstate_i_pkt_start = 1'd0; +reg cdcusbphy_usb_core_txstate_o_pkt_end = 1'd0; +reg [3:0] cdcusbphy_usb_core_txstate_i_pid = 4'd0; +wire [7:0] cdcusbphy_usb_core_txstate_i_data_payload0; +wire cdcusbphy_usb_core_txstate_i_data_ready; +reg cdcusbphy_usb_core_txstate_o_data_ack = 1'd0; +wire cdcusbphy_usb_core_txstate_o_oe12; +reg [3:0] cdcusbphy_usb_core_txstate_pid = 4'd0; +wire [7:0] cdcusbphy_usb_core_txstate_i_data_payload1; +reg cdcusbphy_usb_core_txstate_i_data_strobe = 1'd0; +wire [15:0] cdcusbphy_usb_core_txstate_o_crc; +wire [7:0] cdcusbphy_usb_core_txstate_crc_dat; +reg [15:0] cdcusbphy_usb_core_txstate_crc_cur = 16'd65535; +reg [15:0] cdcusbphy_usb_core_txstate_crc_next = 16'd64770; +wire cdcusbphy_usb_core_txstate_reset; +reg cdcusbphy_usb_core_txstate_is_ongoing0 = 1'd0; +reg cdcusbphy_usb_core_txstate_is_ongoing1 = 1'd0; +reg cdcusbphy_usb_core_rx_reset0 = 1'd0; +wire cdcusbphy_usb_core_rx_o_bit_strobe; +wire cdcusbphy_usb_core_rx_i_usbp; +wire cdcusbphy_usb_core_rx_i_usbn; +wire cdcusbphy_usb_core_rx_o_data_strobe; +wire [7:0] cdcusbphy_usb_core_rx_o_data_payload; +wire cdcusbphy_usb_core_rx_o_pkt_start; +reg cdcusbphy_usb_core_rx_o_pkt_in_progress = 1'd0; +wire cdcusbphy_usb_core_rx_o_pkt_end; +wire [1:0] cdcusbphy_usb_core_rx_dpair; +reg cdcusbphy_usb_core_rx_line_state_dt = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_dj0 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_dk0 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_se00 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_se10 = 1'd0; +reg [1:0] cdcusbphy_usb_core_rx_line_state_phase = 2'd0; +reg cdcusbphy_usb_core_rx_line_state_valid = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_dj1 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_dk1 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_se01 = 1'd0; +reg cdcusbphy_usb_core_rx_line_state_se11 = 1'd0; +wire cdcusbphy_usb_core_rx_o_reset; +reg [6:0] cdcusbphy_usb_core_rx_reset_counter = 7'd0; +wire cdcusbphy_usb_core_rx_nrzi_i_valid; +wire cdcusbphy_usb_core_rx_nrzi_i_dj; +wire cdcusbphy_usb_core_rx_nrzi_i_dk; +wire cdcusbphy_usb_core_rx_nrzi_i_se0; +reg cdcusbphy_usb_core_rx_nrzi_o_valid = 1'd0; +reg cdcusbphy_usb_core_rx_nrzi_o_data = 1'd0; +reg cdcusbphy_usb_core_rx_nrzi_o_se0 = 1'd0; +reg cdcusbphy_usb_core_rx_nrzi_last_data = 1'd0; +wire cdcusbphy_usb_core_rx_reset1; +wire cdcusbphy_usb_core_rx_detect_i_valid; +wire cdcusbphy_usb_core_rx_detect_i_data; +wire cdcusbphy_usb_core_rx_detect_i_se0; +reg cdcusbphy_usb_core_rx_detect_pkt_start = 1'd0; +reg cdcusbphy_usb_core_rx_detect_pkt_active = 1'd0; +reg cdcusbphy_usb_core_rx_detect_pkt_end = 1'd0; +wire cdcusbphy_usb_core_rx_detect_o_pkt_start; +wire cdcusbphy_usb_core_rx_detect_o_pkt_active; +wire cdcusbphy_usb_core_rx_detect_o_pkt_end; +wire cdcusbphy_usb_core_rx_detect_reset; +wire cdcusbphy_usb_core_rx_bitstuff_i_valid; +wire cdcusbphy_usb_core_rx_bitstuff_i_data; +reg cdcusbphy_usb_core_rx_bitstuff_drop_bit = 1'd0; +reg cdcusbphy_usb_core_rx_bitstuff_o_data = 1'd0; +reg cdcusbphy_usb_core_rx_bitstuff_o_error = 1'd0; +reg cdcusbphy_usb_core_rx_bitstuff_o_stall = 1'd1; +wire cdcusbphy_usb_core_rx_bitstuff_reset; +reg cdcusbphy_usb_core_rx_last_reset = 1'd0; +wire cdcusbphy_usb_core_rx_shifter_i_valid; +wire cdcusbphy_usb_core_rx_shifter_i_data; +wire [7:0] cdcusbphy_usb_core_rx_shifter_o_data; +reg cdcusbphy_usb_core_rx_shifter_o_put = 1'd0; +reg [8:0] cdcusbphy_usb_core_rx_shifter_shift_reg = 9'd1; +wire cdcusbphy_usb_core_rx_shifter_reset; +wire cdcusbphy_usb_core_rx_flag_start; +wire cdcusbphy_usb_core_rx_flag_end; +wire cdcusbphy_usb_core_rx_flag_valid; +wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we; +wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable; +wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re; +wire cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable; +wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din; +wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout; +wire cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary = 2'd0; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary = 2'd0; +wire cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary = 2'd0; +reg [1:0] cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain; +wire [1:0] cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain; +wire cdcusbphy_usb_core_rx_payloadFifo_wrport_adr; +wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_r; +wire cdcusbphy_usb_core_rx_payloadFifo_wrport_we; +wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w; +wire cdcusbphy_usb_core_rx_payloadFifo_rdport_adr; +wire [7:0] cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r; +wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we; +wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable; +wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re; +wire cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout; +wire cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary = 2'd0; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary = 2'd0; +wire cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary = 2'd0; +reg [1:0] cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary = 2'd0; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain; +wire cdcusbphy_usb_core_rx_flagsFifo_wrport_adr; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_r; +wire cdcusbphy_usb_core_rx_flagsFifo_wrport_we; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w; +wire cdcusbphy_usb_core_rx_flagsFifo_rdport_adr; +wire [1:0] cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r; +reg [3:0] cdcusbphy_usb_core_o_pid = 4'd0; +reg [6:0] cdcusbphy_usb_core_o_addr = 7'd0; +reg cdcusbphy_usb_core_endp4 = 1'd0; +reg [3:0] cdcusbphy_usb_core_o_endp = 4'd0; +reg [4:0] cdcusbphy_usb_core_crc5 = 5'd0; +reg cdcusbphy_usb_core_o_decoded = 1'd0; +wire cdcusbphy_usb_core_reset0; +wire cdcusbphy_usb_core_usb_reset; +reg cdcusbphy_usb_core_data_recv_put = 1'd0; +wire [7:0] cdcusbphy_usb_core_data_recv_payload; +reg cdcusbphy_usb_core_data_send_get = 1'd0; +reg cdcusbphy_usb_core_data_send_have = 1'd0; +reg [7:0] cdcusbphy_usb_core_data_send_payload = 8'd0; +reg cdcusbphy_usb_core_rdy = 1'd1; +wire cdcusbphy_usb_core_dtb; +reg cdcusbphy_usb_core_arm = 1'd0; +reg cdcusbphy_usb_core_sta = 1'd0; +reg [6:0] cdcusbphy_usb_core_addr = 7'd0; +reg [3:0] cdcusbphy_usb_core_tok = 4'd0; +reg [3:0] cdcusbphy_usb_core_endp = 4'd0; +reg cdcusbphy_usb_core_idle = 1'd0; +reg cdcusbphy_usb_core_start = 1'd0; +reg cdcusbphy_usb_core_poll = 1'd0; +reg cdcusbphy_usb_core_setup = 1'd0; +reg cdcusbphy_usb_core_commit = 1'd0; +reg cdcusbphy_usb_core_retry = 1'd0; +reg cdcusbphy_usb_core_abort = 1'd0; +wire cdcusbphy_usb_core_end; +reg cdcusbphy_usb_core_data_end = 1'd0; +reg cdcusbphy_usb_core_error = 1'd0; +wire cdcusbphy_usb_core_transfer_reset; +reg [3:0] cdcusbphy_usb_core_response_pid = 4'd0; +wire cdcusbphy_usb_core_is_el0; +wire cdcusbphy_usb_core_is_el1; +reg cdcusbphy_pullup_storage = 1'd0; +reg cdcusbphy_pullup_re = 1'd0; +wire cdcusbphy_debug_packet_detected; +wire [29:0] cdcusbphy_debug_bridge_wishbone_adr; +wire [31:0] cdcusbphy_debug_bridge_wishbone_dat_w; +reg [31:0] cdcusbphy_debug_bridge_wishbone_dat_r = 32'd0; +wire [3:0] cdcusbphy_debug_bridge_wishbone_sel; +reg cdcusbphy_debug_bridge_wishbone_cyc = 1'd0; +reg cdcusbphy_debug_bridge_wishbone_stb = 1'd0; +reg cdcusbphy_debug_bridge_wishbone_ack = 1'd0; +reg cdcusbphy_debug_bridge_wishbone_we = 1'd0; +reg cdcusbphy_debug_bridge_wishbone_err = 1'd0; +reg [2:0] cdcusbphy_debug_bridge_byte_counter = 3'd0; +reg cdcusbphy_debug_bridge_byte_counter_reset = 1'd0; +reg cdcusbphy_debug_bridge_byte_counter_ce = 1'd0; +reg cdcusbphy_debug_bridge_cmd = 1'd0; +reg cdcusbphy_debug_bridge_cmd_ce = 1'd0; +reg cdcusbphy_debug_bridge_send_to_wishbone = 1'd0; +wire cdcusbphy_debug_bridge_reply_from_wishbone; +reg cdcusbphy_debug_bridge_transfer_active = 1'd0; +reg [7:0] cdcusbphy_debug_bridge_sink_data = 8'd0; +reg cdcusbphy_debug_bridge_sink_valid = 1'd0; +reg cdcusbphy_debug_bridge_send_ack = 1'd0; +reg cdcusbphy_debug_bridge_n_debug_in_progress = 1'd1; +reg [31:0] cdcusbphy_debug_bridge_address = 32'd0; +reg cdcusbphy_debug_bridge_address_ce = 1'd0; +reg [31:0] cdcusbphy_debug_bridge_data = 32'd0; +reg [31:0] cdcusbphy_debug_bridge_rd_data = 32'd0; +reg cdcusbphy_debug_bridge_rx_data_ce = 1'd0; +reg cdcusbphy_debug_bridge_reset = 1'd0; +wire [6:0] cdcusbphy_csrfield_addr; +reg [6:0] cdcusbphy_csrstorage_storage = 7'd0; +reg cdcusbphy_csrstorage_re = 1'd0; +wire cdcusbphy_address_reset; +reg cdcusbphy_csrfield_in = 1'd0; +reg cdcusbphy_csrfield_out = 1'd0; +reg cdcusbphy_csrfield_setup = 1'd0; +reg cdcusbphy_csrfield_reset = 1'd0; +reg [3:0] cdcusbphy_status = 4'd0; +reg cdcusbphy_setuphandler_reset = 1'd0; +reg cdcusbphy_setuphandler_begin = 1'd0; +reg cdcusbphy_setuphandler_epno = 1'd0; +wire cdcusbphy_setuphandler_usb_reset; +wire [7:0] cdcusbphy_setuphandler_csrfield_data0; +wire [7:0] cdcusbphy_setuphandler_data_status; +reg cdcusbphy_setuphandler_data_we = 1'd0; +reg cdcusbphy_setuphandler_csrfield_reset = 1'd0; +reg [5:0] cdcusbphy_setuphandler_ctrl_storage = 6'd0; +reg cdcusbphy_setuphandler_ctrl_re = 1'd0; +wire [3:0] cdcusbphy_setuphandler_csrfield_epno; +wire cdcusbphy_setuphandler_csrfield_have; +wire cdcusbphy_setuphandler_csrfield_pend; +wire cdcusbphy_setuphandler_csrfield_is_in; +wire cdcusbphy_setuphandler_csrfield_data1; +reg [7:0] cdcusbphy_setuphandler_status_status = 8'd0; +wire cdcusbphy_setuphandler_irq; +wire cdcusbphy_setuphandler_packet_status; +reg cdcusbphy_setuphandler_packet_pending = 1'd0; +wire cdcusbphy_setuphandler_packet_trigger; +reg cdcusbphy_setuphandler_packet_clear = 1'd0; +wire cdcusbphy_setuphandler_reset_status; +reg cdcusbphy_setuphandler_reset_pending = 1'd0; +wire cdcusbphy_setuphandler_reset_trigger; +reg cdcusbphy_setuphandler_reset_clear = 1'd0; +reg cdcusbphy_setuphandler_reset_trigger_d = 1'd0; +wire cdcusbphy_setuphandler_eventmanager_ready0; +wire cdcusbphy_setuphandler_eventmanager_reset0; +reg [1:0] cdcusbphy_setuphandler_eventmanager_status_status = 2'd0; +wire cdcusbphy_setuphandler_eventmanager_ready1; +wire cdcusbphy_setuphandler_eventmanager_reset1; +reg [1:0] cdcusbphy_setuphandler_eventmanager_pending_status = 2'd0; +reg cdcusbphy_setuphandler_eventmanager_pending_re = 1'd0; +reg [1:0] cdcusbphy_setuphandler_eventmanager_pending_r = 2'd0; +wire cdcusbphy_setuphandler_eventmanager_ready2; +wire cdcusbphy_setuphandler_eventmanager_reset2; +reg [1:0] cdcusbphy_setuphandler_eventmanager_enable_storage = 2'd0; +reg cdcusbphy_setuphandler_eventmanager_enable_re = 1'd0; +reg [7:0] cdcusbphy_setuphandler_data_recv_payload = 8'd0; +reg cdcusbphy_setuphandler_data_recv_put = 1'd0; +wire cdcusbphy_setuphandler_setuphandlerinner_re; +reg cdcusbphy_setuphandler_setuphandlerinner_readable = 1'd0; +reg cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we = 1'd0; +wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable; +wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re; +wire cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable; +reg [7:0] cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din = 8'd0; +wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout; +reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_level0 = 4'd0; +reg cdcusbphy_setuphandler_setuphandlerinner_replace = 1'd0; +reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_produce = 4'd0; +reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_consume = 4'd0; +reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_adr = 4'd0; +wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_r; +wire cdcusbphy_setuphandler_setuphandlerinner_wrport_we; +wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w; +wire cdcusbphy_setuphandler_setuphandlerinner_do_read; +wire [3:0] cdcusbphy_setuphandler_setuphandlerinner_rdport_adr; +wire [7:0] cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r; +wire cdcusbphy_setuphandler_setuphandlerinner_rdport_re; +wire [3:0] cdcusbphy_setuphandler_setuphandlerinner_level1; +reg [3:0] cdcusbphy_setuphandler_setuphandlerinner_data_byte = 4'd0; +reg cdcusbphy_setuphandler_setuphandlerinner_have_data_stage = 1'd0; +reg cdcusbphy_setuphandler_setuphandlerinner_is_in = 1'd0; +wire cdcusbphy_setuphandler_setuphandlerinner_empty; +wire cdcusbphy_setuphandler_inner_reset; +wire cdcusbphy_inhandler_dtb; +reg [15:0] cdcusbphy_inhandler_dtbs = 16'd1; +reg [15:0] cdcusbphy_inhandler_stall_status = 16'd0; +wire cdcusbphy_inhandler_syncfifobuffered_re; +reg cdcusbphy_inhandler_syncfifobuffered_readable = 1'd0; +wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_we; +wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable; +wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_re; +wire cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable; +wire [7:0] cdcusbphy_inhandler_syncfifobuffered_syncfifo_din; +wire [7:0] cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout; +reg [6:0] cdcusbphy_inhandler_syncfifobuffered_level0 = 7'd0; +reg cdcusbphy_inhandler_syncfifobuffered_replace = 1'd0; +reg [5:0] cdcusbphy_inhandler_syncfifobuffered_produce = 6'd0; +reg [5:0] cdcusbphy_inhandler_syncfifobuffered_consume = 6'd0; +reg [5:0] cdcusbphy_inhandler_syncfifobuffered_wrport_adr = 6'd0; +wire [7:0] cdcusbphy_inhandler_syncfifobuffered_wrport_dat_r; +wire cdcusbphy_inhandler_syncfifobuffered_wrport_we; +wire [7:0] cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w; +wire cdcusbphy_inhandler_syncfifobuffered_do_read; +wire [5:0] cdcusbphy_inhandler_syncfifobuffered_rdport_adr; +wire [7:0] cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r; +wire cdcusbphy_inhandler_syncfifobuffered_rdport_re; +wire [6:0] cdcusbphy_inhandler_syncfifobuffered_level1; +wire cdcusbphy_inhandler_data_buf_reset; +wire [7:0] cdcusbphy_inhandler_csrfield_data; +reg [7:0] cdcusbphy_inhandler_data_storage = 8'd0; +reg cdcusbphy_inhandler_data_re = 1'd0; +wire [3:0] cdcusbphy_inhandler_csrfield_epno; +reg cdcusbphy_inhandler_csrfield_reset = 1'd0; +reg cdcusbphy_inhandler_csrfield_stall = 1'd0; +reg [6:0] cdcusbphy_inhandler_ctrl_storage = 7'd0; +reg cdcusbphy_inhandler_ctrl_re = 1'd0; +wire cdcusbphy_inhandler_csrfield_idle; +wire cdcusbphy_inhandler_csrfield_have; +wire cdcusbphy_inhandler_csrfield_pend; +reg [5:0] cdcusbphy_inhandler_status_status0 = 6'd0; +wire cdcusbphy_inhandler_irq; +wire cdcusbphy_inhandler_packet_status; +reg cdcusbphy_inhandler_packet_pending = 1'd0; +wire cdcusbphy_inhandler_packet_trigger; +reg cdcusbphy_inhandler_packet_clear = 1'd0; +wire cdcusbphy_inhandler_done0; +wire cdcusbphy_inhandler_status_status1; +wire cdcusbphy_inhandler_done1; +wire cdcusbphy_inhandler_pending_status; +reg cdcusbphy_inhandler_pending_re = 1'd0; +reg cdcusbphy_inhandler_pending_r = 1'd0; +wire cdcusbphy_inhandler_done2; +reg cdcusbphy_inhandler_enable_storage = 1'd0; +reg cdcusbphy_inhandler_enable_re = 1'd0; +wire [15:0] cdcusbphy_inhandler_ep_stall_mask; +wire cdcusbphy_inhandler_stalled; +wire cdcusbphy_inhandler_response; +reg cdcusbphy_inhandler_queued = 1'd0; +reg cdcusbphy_inhandler_was_queued = 1'd0; +reg cdcusbphy_inhandler_transmitted = 1'd0; +reg cdcusbphy_inhandler_dtb_reset = 1'd0; +wire [7:0] cdcusbphy_inhandler_data_out; +wire cdcusbphy_inhandler_data_out_have; +reg cdcusbphy_inhandler_data_out_advance = 1'd0; +wire cdcusbphy_inhandler_is_our_packet; +wire cdcusbphy_inhandler_is_in_packet; +wire cdcusbphy_outhandler_syncfifobuffered_re; +reg cdcusbphy_outhandler_syncfifobuffered_readable = 1'd0; +wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_we; +wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable; +wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_re; +wire cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable; +wire [7:0] cdcusbphy_outhandler_syncfifobuffered_syncfifo_din; +wire [7:0] cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout; +reg [6:0] cdcusbphy_outhandler_syncfifobuffered_level0 = 7'd0; +reg cdcusbphy_outhandler_syncfifobuffered_replace = 1'd0; +reg [6:0] cdcusbphy_outhandler_syncfifobuffered_produce = 7'd0; +reg [6:0] cdcusbphy_outhandler_syncfifobuffered_consume = 7'd0; +reg [6:0] cdcusbphy_outhandler_syncfifobuffered_wrport_adr = 7'd0; +wire [7:0] cdcusbphy_outhandler_syncfifobuffered_wrport_dat_r; +wire cdcusbphy_outhandler_syncfifobuffered_wrport_we; +wire [7:0] cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w; +wire cdcusbphy_outhandler_syncfifobuffered_do_read; +wire [6:0] cdcusbphy_outhandler_syncfifobuffered_rdport_adr; +wire [7:0] cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r; +wire cdcusbphy_outhandler_syncfifobuffered_rdport_re; +wire [6:0] cdcusbphy_outhandler_syncfifobuffered_level1; +wire cdcusbphy_outhandler_data_buf_reset; +wire [7:0] cdcusbphy_outhandler_csrfield_data; +wire [7:0] cdcusbphy_outhandler_data_status; +reg cdcusbphy_outhandler_data_we = 1'd0; +wire [3:0] cdcusbphy_outhandler_csrfield_epno0; +wire cdcusbphy_outhandler_csrfield_enable; +reg cdcusbphy_outhandler_csrfield_reset = 1'd0; +wire cdcusbphy_outhandler_csrfield_stall; +reg [6:0] cdcusbphy_outhandler_ctrl_storage = 7'd0; +reg cdcusbphy_outhandler_ctrl_re = 1'd0; +wire [3:0] cdcusbphy_outhandler_csrfield_epno1; +wire cdcusbphy_outhandler_csrfield_have; +wire cdcusbphy_outhandler_csrfield_pend; +reg [5:0] cdcusbphy_outhandler_status_status0 = 6'd0; +wire cdcusbphy_outhandler_irq; +wire cdcusbphy_outhandler_packet_status; +reg cdcusbphy_outhandler_packet_pending = 1'd0; +wire cdcusbphy_outhandler_packet_trigger; +reg cdcusbphy_outhandler_packet_clear = 1'd0; +wire cdcusbphy_outhandler_done0; +wire cdcusbphy_outhandler_status_status1; +wire cdcusbphy_outhandler_done1; +wire cdcusbphy_outhandler_pending_status; +reg cdcusbphy_outhandler_pending_re = 1'd0; +reg cdcusbphy_outhandler_pending_r = 1'd0; +wire cdcusbphy_outhandler_done2; +reg cdcusbphy_outhandler_enable_storage = 1'd0; +reg cdcusbphy_outhandler_enable_re = 1'd0; +reg cdcusbphy_outhandler_usb_reset = 1'd0; +wire cdcusbphy_outhandler_stalled; +wire cdcusbphy_outhandler_enabled; +reg [15:0] cdcusbphy_outhandler_stall_status = 16'd0; +reg [15:0] cdcusbphy_outhandler_enable_status = 16'd0; +reg [15:0] cdcusbphy_outhandler_ep_mask = 16'd1; +reg [3:0] cdcusbphy_outhandler_epno = 4'd0; +wire cdcusbphy_outhandler_response; +reg cdcusbphy_outhandler_responding = 1'd0; +wire cdcusbphy_outhandler_is_out_packet; +reg [7:0] cdcusbphy_outhandler_data_recv_payload = 8'd0; +reg cdcusbphy_outhandler_data_recv_put = 1'd0; +wire cdcusbphy_ev_irq; +reg cdcusbphy_in_next = 1'd0; +reg cdcusbphy_out_next = 1'd0; +reg cdcusbphy_usb_core_reset1 = 1'd0; +wire cdcusbphy_resetinserter_reset; +wire cdcusbphy_csrtransform_pullup_out_re; +wire cdcusbphy_csrtransform; +reg cdcusbphy_csrtransform_address_re = 1'd0; +reg [6:0] cdcusbphy_csrtransform_address_addr0 = 7'd0; +reg cdcusbphy_csrtransform_setup_ctrl_re = 1'd0; +reg cdcusbphy_csrtransform_setup_ctrl_reset0 = 1'd0; +reg cdcusbphy_csrtransform_setup_ev_enable_re = 1'd0; +reg cdcusbphy_csrtransform_setup_ev_enable_ready0 = 1'd0; +reg cdcusbphy_csrtransform_setup_ev_enable_reset0 = 1'd0; +reg cdcusbphy_csrtransform_in_data_re = 1'd0; +reg [7:0] cdcusbphy_csrtransform_in_data_data0 = 8'd0; +reg cdcusbphy_csrtransform_in_ctrl_re = 1'd0; +reg [3:0] cdcusbphy_csrtransform_in_ctrl_epno0 = 4'd0; +reg cdcusbphy_csrtransform_in_ctrl_reset0 = 1'd0; +reg cdcusbphy_csrtransform_in_ctrl_stall0 = 1'd0; +reg cdcusbphy_csrtransform_in_ev_enable_re = 1'd0; +reg cdcusbphy_csrtransform_in_ev_enable_done0 = 1'd0; +reg cdcusbphy_csrtransform_out_ctrl_re = 1'd0; +reg [3:0] cdcusbphy_csrtransform_out_ctrl_epno0 = 4'd0; +reg cdcusbphy_csrtransform_out_ctrl_enable0 = 1'd0; +reg cdcusbphy_csrtransform_out_ctrl_reset0 = 1'd0; +reg cdcusbphy_csrtransform_out_ctrl_stall0 = 1'd0; +reg cdcusbphy_csrtransform_out_ev_enable_re = 1'd0; +reg cdcusbphy_csrtransform_out_ev_enable_done0 = 1'd0; +reg cdcusbphy_sink_valid = 1'd0; +wire cdcusbphy_sink_ready; +reg cdcusbphy_sink_first = 1'd0; +reg cdcusbphy_sink_last = 1'd0; +reg [7:0] cdcusbphy_sink_payload_data = 8'd0; +wire cdcusbphy_source_valid; +reg cdcusbphy_source_ready = 1'd0; +wire cdcusbphy_source_first; +wire cdcusbphy_source_last; +wire [7:0] cdcusbphy_source_payload_data; +reg cdcusbphy_rts = 1'd0; +reg cdcusbphy_dtr = 1'd0; +wire [7:0] cdcusbphy_adr; +wire [7:0] cdcusbphy_dat_r; +reg [8:0] cdcusbphy_response_addr = 9'd0; +reg [5:0] cdcusbphy_response_len = 6'd0; +reg [5:0] cdcusbphy_bytes_remaining = 6'd0; +reg [8:0] cdcusbphy_bytes_addr = 9'd0; +reg [6:0] cdcusbphy_new_address = 7'd0; +wire cdcusbphy_configured; +reg [15:0] cdcusbphy_configured_delay = 16'd65535; +wire cdcusbphy_configure_set; +reg [31:0] cdcusbphy_usbPacket = 32'd0; +wire [15:0] cdcusbphy_wRequestAndType; +wire [15:0] cdcusbphy_wValue; +reg [7:0] cdcusbphy_wLength = 8'd0; +reg [3:0] cdcusbphy_setup_index = 4'd0; +reg cdcusbphy_delayed_re = 1'd0; +reg [7:0] cdcusbphy_data_d1 = 8'd0; +reg cdcusbphy_re_d1 = 1'd0; +reg [7:0] cdcusbphy_data_d2 = 8'd0; +reg cdcusbphy_re_d2 = 1'd0; +reg rxtx_re = 1'd0; +wire [7:0] rxtx_r; +reg rxtx_we = 1'd0; +wire [7:0] rxtx_w; +wire txfull_status; +wire txfull_we; +reg txfull_re = 1'd0; +wire rxempty_status; +wire rxempty_we; +reg rxempty_re = 1'd0; +wire irq; +wire tx_status; +reg tx_pending = 1'd0; +wire tx_trigger; +reg tx_clear = 1'd0; +reg tx_trigger_d = 1'd0; +wire rx_status; +reg rx_pending = 1'd0; +wire rx_trigger; +reg rx_clear = 1'd0; +reg rx_trigger_d = 1'd0; +wire tx0; +wire rx0; +reg [1:0] status_status = 2'd0; +wire status_we; +reg status_re = 1'd0; +wire tx1; +wire rx1; +reg [1:0] pending_status = 2'd0; +wire pending_we; +reg pending_re = 1'd0; +reg [1:0] pending_r = 2'd0; +wire tx2; +wire rx2; +reg [1:0] enable_storage = 2'd0; +reg enable_re = 1'd0; +reg [31:0] tuning_word_storage = 32'd0; +reg tuning_word_re = 1'd0; +reg configured_re = 1'd0; +wire configured_r; +reg configured_we = 1'd0; +reg configured_w = 1'd0; +wire sink_sink_valid; +wire sink_sink_ready; +wire sink_sink_first; +wire sink_sink_last; +wire [7:0] sink_sink_payload_data; +wire source_source_valid; +wire source_source_ready; +wire source_source_first; +wire source_source_last; +wire [7:0] source_source_payload_data; +wire rts; +wire dtr; +wire async_rst; +wire i; +wire o; +reg toggle_i = 1'd0; +wire toggle_o; +reg toggle_o_r = 1'd0; +wire asyncfifo0_sink_valid; +wire asyncfifo0_sink_ready; +reg asyncfifo0_sink_first = 1'd0; +reg asyncfifo0_sink_last = 1'd0; +wire [7:0] asyncfifo0_sink_payload_data; +wire asyncfifo0_source_valid; +wire asyncfifo0_source_ready; +wire asyncfifo0_source_first; +wire asyncfifo0_source_last; +wire [7:0] asyncfifo0_source_payload_data; +wire asyncfifo0_asyncfifo0_we; +wire asyncfifo0_asyncfifo0_writable; +wire asyncfifo0_asyncfifo0_re; +wire asyncfifo0_asyncfifo0_readable; +wire [9:0] asyncfifo0_asyncfifo0_din; +wire [9:0] asyncfifo0_asyncfifo0_dout; +wire asyncfifo0_graycounter0_ce; +reg [2:0] asyncfifo0_graycounter0_q = 3'd0; +wire [2:0] asyncfifo0_graycounter0_q_next; +reg [2:0] asyncfifo0_graycounter0_q_binary = 3'd0; +reg [2:0] asyncfifo0_graycounter0_q_next_binary = 3'd0; +wire asyncfifo0_graycounter1_ce; +reg [2:0] asyncfifo0_graycounter1_q = 3'd0; +wire [2:0] asyncfifo0_graycounter1_q_next; +reg [2:0] asyncfifo0_graycounter1_q_binary = 3'd0; +reg [2:0] asyncfifo0_graycounter1_q_next_binary = 3'd0; +wire [2:0] asyncfifo0_produce_rdomain; +wire [2:0] asyncfifo0_consume_wdomain; +wire [1:0] asyncfifo0_wrport_adr; +wire [9:0] asyncfifo0_wrport_dat_r; +wire asyncfifo0_wrport_we; +wire [9:0] asyncfifo0_wrport_dat_w; +wire [1:0] asyncfifo0_rdport_adr; +wire [9:0] asyncfifo0_rdport_dat_r; +wire [7:0] asyncfifo0_fifo_in_payload_data; +wire asyncfifo0_fifo_in_first; +wire asyncfifo0_fifo_in_last; +wire [7:0] asyncfifo0_fifo_out_payload_data; +wire asyncfifo0_fifo_out_first; +wire asyncfifo0_fifo_out_last; +wire asyncfifo1_sink_valid; +wire asyncfifo1_sink_ready; +wire asyncfifo1_sink_first; +wire asyncfifo1_sink_last; +wire [7:0] asyncfifo1_sink_payload_data; +wire asyncfifo1_source_valid; +wire asyncfifo1_source_ready; +wire asyncfifo1_source_first; +wire asyncfifo1_source_last; +wire [7:0] asyncfifo1_source_payload_data; +wire asyncfifo1_asyncfifo1_we; +wire asyncfifo1_asyncfifo1_writable; +wire asyncfifo1_asyncfifo1_re; +wire asyncfifo1_asyncfifo1_readable; +wire [9:0] asyncfifo1_asyncfifo1_din; +wire [9:0] asyncfifo1_asyncfifo1_dout; +wire asyncfifo1_graycounter2_ce; +reg [2:0] asyncfifo1_graycounter2_q = 3'd0; +wire [2:0] asyncfifo1_graycounter2_q_next; +reg [2:0] asyncfifo1_graycounter2_q_binary = 3'd0; +reg [2:0] asyncfifo1_graycounter2_q_next_binary = 3'd0; +wire asyncfifo1_graycounter3_ce; +reg [2:0] asyncfifo1_graycounter3_q = 3'd0; +wire [2:0] asyncfifo1_graycounter3_q_next; +reg [2:0] asyncfifo1_graycounter3_q_binary = 3'd0; +reg [2:0] asyncfifo1_graycounter3_q_next_binary = 3'd0; +wire [2:0] asyncfifo1_produce_rdomain; +wire [2:0] asyncfifo1_consume_wdomain; +wire [1:0] asyncfifo1_wrport_adr; +wire [9:0] asyncfifo1_wrport_dat_r; +wire asyncfifo1_wrport_we; +wire [9:0] asyncfifo1_wrport_dat_w; +wire [1:0] asyncfifo1_rdport_adr; +wire [9:0] asyncfifo1_rdport_dat_r; +wire [7:0] asyncfifo1_fifo_in_payload_data; +wire asyncfifo1_fifo_in_first; +wire asyncfifo1_fifo_in_last; +wire [7:0] asyncfifo1_fifo_out_payload_data; +wire asyncfifo1_fifo_out_first; +wire asyncfifo1_fifo_out_last; +wire [29:0] wb_ctrl_adr; +wire [31:0] wb_ctrl_dat_w; +wire [31:0] wb_ctrl_dat_r; +wire [3:0] wb_ctrl_sel; +wire wb_ctrl_cyc; +wire wb_ctrl_stb; +wire wb_ctrl_ack; +wire wb_ctrl_we; +wire [2:0] wb_ctrl_cti; +wire [1:0] wb_ctrl_bte; +wire wb_ctrl_err; +reg [1:0] subfragments_fsm_state = 2'd0; +reg [1:0] subfragments_fsm_next_state = 2'd0; +reg [7:0] cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 = 8'd0; +reg cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 = 1'd0; +reg [1:0] cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 = 2'd0; +reg cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 = 1'd0; +reg [2:0] subfragments_resetinserter_state = 3'd0; +reg [2:0] subfragments_resetinserter_next_state = 3'd0; +reg [2:0] subfragments_txnrziencoder_state = 3'd0; +reg [2:0] subfragments_txnrziencoder_next_state = 3'd0; +reg [3:0] subfragments_txpacketsend_state = 4'd0; +reg [3:0] subfragments_txpacketsend_next_state = 4'd0; +reg cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 = 1'd0; +reg cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 = 1'd0; +reg [3:0] cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 = 4'd0; +reg cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 = 1'd0; +reg [2:0] subfragments_rxpipeline_state = 3'd0; +reg [2:0] subfragments_rxpipeline_next_state = 3'd0; +reg [2:0] subfragments_rxpipeline_rxpacketdetect_state = 3'd0; +reg [2:0] subfragments_rxpipeline_rxpacketdetect_next_state = 3'd0; +reg [2:0] subfragments_rxpipeline_rxbitstuffremover_state = 3'd0; +reg [2:0] subfragments_rxpipeline_rxbitstuffremover_next_state = 3'd0; +reg [2:0] subfragments_packetheaderdecode_state = 3'd0; +reg [2:0] subfragments_packetheaderdecode_next_state = 3'd0; +reg [3:0] cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 = 4'd0; +reg cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 = 1'd0; +reg [6:0] subfragments_packetheaderdecode_next_value = 7'd0; +reg subfragments_packetheaderdecode_next_value_ce = 1'd0; +reg cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 = 1'd0; +reg cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 = 1'd0; +reg [3:0] cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 = 4'd0; +reg cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 = 1'd0; +reg [4:0] cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 = 5'd0; +reg cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 = 1'd0; +reg [3:0] subfragments_clockdomainsrenamer_state0 = 4'd1; +reg [3:0] subfragments_clockdomainsrenamer_next_state0 = 4'd0; +reg [3:0] cdcusbphy_usb_core_tok_csrtransform_f_next_value0 = 4'd0; +reg cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 = 1'd0; +reg [3:0] cdcusbphy_usb_core_endp_csrtransform_f_next_value1 = 4'd0; +reg cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 = 1'd0; +reg [3:0] cdcusbphy_usb_core_response_pid_csrtransform_t_next_value = 4'd0; +reg cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce = 1'd0; +reg [3:0] subfragments_usbwishbonebridge_state = 4'd0; +reg [3:0] subfragments_usbwishbonebridge_next_state = 4'd0; +reg [2:0] subfragments_clockdomainsrenamer_state1 = 3'd0; +reg [2:0] subfragments_clockdomainsrenamer_next_state1 = 3'd0; +reg [6:0] cdcusbphy_usb_core_addr_csrtransform_next_value = 7'd0; +reg cdcusbphy_usb_core_addr_csrtransform_next_value_ce = 1'd0; +reg [2:0] subfragments_state = 3'd0; +reg [2:0] subfragments_next_state = 3'd0; +reg [3:0] cdcusbphy_setup_index_fsm_next_value0 = 4'd0; +reg cdcusbphy_setup_index_fsm_next_value_ce0 = 1'd0; +reg cdcusbphy_delayed_re_fsm_next_value1 = 1'd0; +reg cdcusbphy_delayed_re_fsm_next_value_ce1 = 1'd0; +reg [7:0] cdcusbphy_data_d1_fsm_t_next_value0 = 8'd0; +reg cdcusbphy_data_d1_fsm_t_next_value_ce0 = 1'd0; +reg [7:0] cdcusbphy_data_d2_fsm_t_next_value1 = 8'd0; +reg cdcusbphy_data_d2_fsm_t_next_value_ce1 = 1'd0; +reg cdcusbphy_re_d1_fsm_t_next_value2 = 1'd0; +reg cdcusbphy_re_d1_fsm_t_next_value_ce2 = 1'd0; +reg cdcusbphy_re_d2_fsm_t_next_value3 = 1'd0; +reg cdcusbphy_re_d2_fsm_t_next_value_ce3 = 1'd0; +reg [31:0] cdcusbphy_usbPacket_fsm_cases_next_value0 = 32'd0; +reg cdcusbphy_usbPacket_fsm_cases_next_value_ce0 = 1'd0; +reg [7:0] cdcusbphy_wLength_fsm_cases_next_value1 = 8'd0; +reg cdcusbphy_wLength_fsm_cases_next_value_ce1 = 1'd0; +reg [6:0] cdcusbphy_new_address_fsm_t_next_value4 = 7'd0; +reg cdcusbphy_new_address_fsm_t_next_value_ce4 = 1'd0; +reg cdcusbphy_rts_fsm_t_next_value5 = 1'd0; +reg cdcusbphy_rts_fsm_t_next_value_ce5 = 1'd0; +reg cdcusbphy_dtr_fsm_t_next_value6 = 1'd0; +reg cdcusbphy_dtr_fsm_t_next_value_ce6 = 1'd0; +reg [5:0] cdcusbphy_bytes_remaining_fsm_f_next_value0 = 6'd0; +reg cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 = 1'd0; +reg [8:0] cdcusbphy_bytes_addr_fsm_f_next_value1 = 9'd0; +reg cdcusbphy_bytes_addr_fsm_f_next_value_ce1 = 1'd0; +reg [13:0] basesoc_basesoc_adr = 14'd0; +reg basesoc_basesoc_we = 1'd0; +reg [31:0] basesoc_basesoc_dat_w = 32'd0; +wire [31:0] basesoc_basesoc_dat_r; +wire [29:0] basesoc_basesoc_wishbone_adr; +wire [31:0] basesoc_basesoc_wishbone_dat_w; +reg [31:0] basesoc_basesoc_wishbone_dat_r = 32'd0; +wire [3:0] basesoc_basesoc_wishbone_sel; +wire basesoc_basesoc_wishbone_cyc; +wire basesoc_basesoc_wishbone_stb; +reg basesoc_basesoc_wishbone_ack = 1'd0; +wire basesoc_basesoc_wishbone_we; +wire [2:0] basesoc_basesoc_wishbone_cti; +wire [1:0] basesoc_basesoc_wishbone_bte; +reg basesoc_basesoc_wishbone_err = 1'd0; +wire [13:0] basesoc_interface0_bank_bus_adr; +wire basesoc_interface0_bank_bus_we; +wire [31:0] basesoc_interface0_bank_bus_dat_w; +reg [31:0] basesoc_interface0_bank_bus_dat_r = 32'd0; +reg basesoc_csrbank0_reset0_re = 1'd0; +wire [1:0] basesoc_csrbank0_reset0_r; +reg basesoc_csrbank0_reset0_we = 1'd0; +wire [1:0] basesoc_csrbank0_reset0_w; +reg basesoc_csrbank0_scratch0_re = 1'd0; +wire [31:0] basesoc_csrbank0_scratch0_r; +reg basesoc_csrbank0_scratch0_we = 1'd0; +wire [31:0] basesoc_csrbank0_scratch0_w; +reg basesoc_csrbank0_bus_errors_re = 1'd0; +wire [31:0] basesoc_csrbank0_bus_errors_r; +reg basesoc_csrbank0_bus_errors_we = 1'd0; +wire [31:0] basesoc_csrbank0_bus_errors_w; +wire basesoc_csrbank0_sel; +wire [13:0] basesoc_interface1_bank_bus_adr; +wire basesoc_interface1_bank_bus_we; +wire [31:0] basesoc_interface1_bank_bus_dat_w; +reg [31:0] basesoc_interface1_bank_bus_dat_r = 32'd0; +reg basesoc_csrbank1_txfull_re = 1'd0; +wire basesoc_csrbank1_txfull_r; +reg basesoc_csrbank1_txfull_we = 1'd0; +wire basesoc_csrbank1_txfull_w; +reg basesoc_csrbank1_rxempty_re = 1'd0; +wire basesoc_csrbank1_rxempty_r; +reg basesoc_csrbank1_rxempty_we = 1'd0; +wire basesoc_csrbank1_rxempty_w; +reg basesoc_csrbank1_ev_status_re = 1'd0; +wire [1:0] basesoc_csrbank1_ev_status_r; +reg basesoc_csrbank1_ev_status_we = 1'd0; +wire [1:0] basesoc_csrbank1_ev_status_w; +reg basesoc_csrbank1_ev_pending_re = 1'd0; +wire [1:0] basesoc_csrbank1_ev_pending_r; +reg basesoc_csrbank1_ev_pending_we = 1'd0; +wire [1:0] basesoc_csrbank1_ev_pending_w; +reg basesoc_csrbank1_ev_enable0_re = 1'd0; +wire [1:0] basesoc_csrbank1_ev_enable0_r; +reg basesoc_csrbank1_ev_enable0_we = 1'd0; +wire [1:0] basesoc_csrbank1_ev_enable0_w; +reg basesoc_csrbank1_tuning_word0_re = 1'd0; +wire [31:0] basesoc_csrbank1_tuning_word0_r; +reg basesoc_csrbank1_tuning_word0_we = 1'd0; +wire [31:0] basesoc_csrbank1_tuning_word0_w; +wire basesoc_csrbank1_sel; +wire [13:0] basesoc_csr_interconnect_adr; +wire basesoc_csr_interconnect_we; +wire [31:0] basesoc_csr_interconnect_dat_w; +wire [31:0] basesoc_csr_interconnect_dat_r; +reg basesoc_state = 1'd0; +reg basesoc_next_state = 1'd0; +wire [8:0] slice_proxy; +wire inferedsdrtristate0__o; +reg inferedsdrtristate0_oe = 1'd0; +wire inferedsdrtristate0__i; +wire sdrio_clk; +wire inferedsdrtristate1__o; +reg inferedsdrtristate1_oe = 1'd0; +wire inferedsdrtristate1__i; +wire sdrio_clk_1; +reg multiregimpl0_regs0 = 1'd0; +reg multiregimpl0_regs1 = 1'd0; +reg multiregimpl0_regs2 = 1'd0; +reg multiregimpl1_regs0 = 1'd0; +reg multiregimpl1_regs1 = 1'd0; +reg multiregimpl1_regs2 = 1'd0; +reg multiregimpl2_regs = 1'd0; +reg [1:0] multiregimpl3_regs0 = 2'd0; +reg [1:0] multiregimpl3_regs1 = 2'd0; +reg [1:0] multiregimpl4_regs0 = 2'd0; +reg [1:0] multiregimpl4_regs1 = 2'd0; +reg [1:0] multiregimpl5_regs0 = 2'd0; +reg [1:0] multiregimpl5_regs1 = 2'd0; +reg [1:0] multiregimpl6_regs0 = 2'd0; +reg [1:0] multiregimpl6_regs1 = 2'd0; +reg multiregimpl7_regs0 = 1'd0; +reg multiregimpl7_regs1 = 1'd0; +reg multiregimpl8_regs0 = 1'd0; +reg multiregimpl8_regs1 = 1'd0; +reg multiregimpl9_regs0 = 1'd0; +reg multiregimpl9_regs1 = 1'd0; +reg [2:0] multiregimpl10_regs0 = 3'd0; +reg [2:0] multiregimpl10_regs1 = 3'd0; +reg [2:0] multiregimpl11_regs0 = 3'd0; +reg [2:0] multiregimpl11_regs1 = 3'd0; +reg [2:0] multiregimpl12_regs0 = 3'd0; +reg [2:0] multiregimpl12_regs1 = 3'd0; +reg [2:0] multiregimpl13_regs0 = 3'd0; +reg [2:0] multiregimpl13_regs1 = 3'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign usb_tx_en = usb_iobuf_usb_tx_en; +assign interrupt = irq; +assign wb_ctrl_adr = wishbone_adr; +assign wb_ctrl_dat_w = wishbone_dat_w; +assign wishbone_dat_r = wb_ctrl_dat_r; +assign wb_ctrl_sel = wishbone_sel; +assign wb_ctrl_cyc = wishbone_cyc; +assign wb_ctrl_stb = wishbone_stb; +assign wishbone_ack = wb_ctrl_ack; +assign wb_ctrl_we = wishbone_we; +assign wb_ctrl_cti = wishbone_cti; +assign wb_ctrl_bte = wishbone_bte; +assign wishbone_err = wb_ctrl_err; +assign usb_48_clk = clk_clk48; +assign usb_48_to_12_clk = clk_clk48; +assign crg_clk12 = crg_clk12_counter[1]; +assign sys_clk = clk_clksys; +assign usb_12_clk = crg_clk12; +assign sys_rst = reset; +assign usb_12_rst = reset; +assign usb_48_rst = reset; +assign bus_errors_status = bus_errors; +assign cdcusbphy_source_valid = source_source_valid; +assign source_source_ready = cdcusbphy_source_ready; +assign cdcusbphy_source_first = source_source_first; +assign cdcusbphy_source_last = source_source_last; +assign cdcusbphy_source_payload_data = source_source_payload_data; +assign sink_sink_valid = cdcusbphy_sink_valid; +assign cdcusbphy_sink_ready = sink_sink_ready; +assign sink_sink_first = cdcusbphy_sink_first; +assign sink_sink_last = cdcusbphy_sink_last; +assign sink_sink_payload_data = cdcusbphy_sink_payload_data; +assign async_rst = cdcusbphy_dtr; +assign i = configured_re; +assign cdcusbphy_configure_set = o; +assign asyncfifo0_sink_valid = rxtx_re; +assign asyncfifo0_sink_payload_data = rxtx_r; +assign txfull_status = (~asyncfifo0_sink_ready); +assign source_source_valid = asyncfifo0_source_valid; +assign asyncfifo0_source_ready = source_source_ready; +assign source_source_first = asyncfifo0_source_first; +assign source_source_last = asyncfifo0_source_last; +assign source_source_payload_data = asyncfifo0_source_payload_data; +assign tx_trigger = (~asyncfifo0_sink_ready); +assign asyncfifo1_sink_valid = sink_sink_valid; +assign sink_sink_ready = asyncfifo1_sink_ready; +assign asyncfifo1_sink_first = sink_sink_first; +assign asyncfifo1_sink_last = sink_sink_last; +assign asyncfifo1_sink_payload_data = sink_sink_payload_data; +assign rxempty_status = (~asyncfifo1_source_valid); +assign rxtx_w = asyncfifo1_source_payload_data; +assign asyncfifo1_source_ready = (rx_clear | (1'd0 & rxtx_we)); +assign rx_trigger = (~asyncfifo1_source_valid); +assign cdcusbphy_csrtransform = (~usb_12_rst); +assign cdcusbphy_csrtransform_pullup_out_re = 1'd1; +assign cdcusbphy_configured = (cdcusbphy_configured_delay == 1'd0); +assign cdcusbphy_wRequestAndType = cdcusbphy_usbPacket[31:16]; +assign cdcusbphy_wValue = cdcusbphy_usbPacket[15:0]; +always @(*) begin + cdcusbphy_response_addr <= 9'd0; + cdcusbphy_response_len <= 6'd0; + case (cdcusbphy_usbPacket) + 20'd590080: begin + cdcusbphy_response_len <= 1'd0; + cdcusbphy_response_addr <= 8'd242; + end + 32'd2147483648: begin + cdcusbphy_response_len <= 2'd2; + cdcusbphy_response_addr <= 8'd240; + end + 32'd2147876865: begin + cdcusbphy_response_len <= 5'd18; + cdcusbphy_response_addr <= 6'd63; + end + 32'd2147876866: begin + cdcusbphy_response_len <= 6'd62; + cdcusbphy_response_addr <= 1'd1; + end + 32'd2147876867: begin + cdcusbphy_response_len <= 3'd4; + cdcusbphy_response_addr <= 7'd81; + end + 32'd2147876879: begin + cdcusbphy_response_len <= 5'd29; + cdcusbphy_response_addr <= 8'd153; + end + 32'd2147877123: begin + cdcusbphy_response_len <= 5'd20; + cdcusbphy_response_addr <= 7'd85; + end + 32'd2147877379: begin + cdcusbphy_response_len <= 6'd48; + cdcusbphy_response_addr <= 7'd105; + end + 32'd2147937795: begin + cdcusbphy_response_len <= 5'd18; + cdcusbphy_response_addr <= 8'd182; + end + 32'd2703294464: begin + cdcusbphy_response_len <= 3'd7; + cdcusbphy_response_addr <= 8'd242; + end + 32'd3229483008: begin + cdcusbphy_response_len <= 6'd40; + cdcusbphy_response_addr <= 8'd200; + end + endcase +end +assign cdcusbphy_adr = cdcusbphy_bytes_addr; +assign cdcusbphy_csrfield_addr = cdcusbphy_csrstorage_storage[6:0]; +always @(*) begin + cdcusbphy_status <= 4'd0; + cdcusbphy_status[0] <= cdcusbphy_csrfield_in; + cdcusbphy_status[1] <= cdcusbphy_csrfield_out; + cdcusbphy_status[2] <= cdcusbphy_csrfield_setup; + cdcusbphy_status[3] <= cdcusbphy_csrfield_reset; +end +assign cdcusbphy_setuphandler_data_status[7:0] = cdcusbphy_setuphandler_csrfield_data0; +always @(*) begin + cdcusbphy_setuphandler_csrfield_reset <= 1'd0; + if (cdcusbphy_setuphandler_ctrl_re) begin + cdcusbphy_setuphandler_csrfield_reset <= cdcusbphy_setuphandler_ctrl_storage[5]; + end +end +always @(*) begin + cdcusbphy_setuphandler_status_status <= 8'd0; + cdcusbphy_setuphandler_status_status[3:0] <= cdcusbphy_setuphandler_csrfield_epno; + cdcusbphy_setuphandler_status_status[4] <= cdcusbphy_setuphandler_csrfield_have; + cdcusbphy_setuphandler_status_status[5] <= cdcusbphy_setuphandler_csrfield_pend; + cdcusbphy_setuphandler_status_status[6] <= cdcusbphy_setuphandler_csrfield_is_in; + cdcusbphy_setuphandler_status_status[7] <= cdcusbphy_setuphandler_csrfield_data1; +end +always @(*) begin + cdcusbphy_setuphandler_eventmanager_status_status <= 2'd0; + cdcusbphy_setuphandler_eventmanager_status_status[0] <= cdcusbphy_setuphandler_eventmanager_ready0; + cdcusbphy_setuphandler_eventmanager_status_status[1] <= cdcusbphy_setuphandler_eventmanager_reset0; +end +always @(*) begin + cdcusbphy_setuphandler_eventmanager_pending_status <= 2'd0; + cdcusbphy_setuphandler_eventmanager_pending_status[0] <= cdcusbphy_setuphandler_eventmanager_ready1; + cdcusbphy_setuphandler_eventmanager_pending_status[1] <= cdcusbphy_setuphandler_eventmanager_reset1; +end +assign cdcusbphy_setuphandler_eventmanager_ready2 = cdcusbphy_setuphandler_eventmanager_enable_storage[0]; +assign cdcusbphy_setuphandler_eventmanager_reset2 = cdcusbphy_setuphandler_eventmanager_enable_storage[1]; +assign cdcusbphy_inhandler_csrfield_data = cdcusbphy_inhandler_data_storage[7:0]; +assign cdcusbphy_inhandler_csrfield_epno = cdcusbphy_inhandler_ctrl_storage[3:0]; +always @(*) begin + cdcusbphy_inhandler_csrfield_reset <= 1'd0; + if (cdcusbphy_inhandler_ctrl_re) begin + cdcusbphy_inhandler_csrfield_reset <= cdcusbphy_inhandler_ctrl_storage[5]; + end +end +always @(*) begin + cdcusbphy_inhandler_csrfield_stall <= 1'd0; + if (cdcusbphy_inhandler_ctrl_re) begin + cdcusbphy_inhandler_csrfield_stall <= cdcusbphy_inhandler_ctrl_storage[6]; + end +end +always @(*) begin + cdcusbphy_inhandler_status_status0 <= 6'd0; + cdcusbphy_inhandler_status_status0[0] <= cdcusbphy_inhandler_csrfield_idle; + cdcusbphy_inhandler_status_status0[4] <= cdcusbphy_inhandler_csrfield_have; + cdcusbphy_inhandler_status_status0[5] <= cdcusbphy_inhandler_csrfield_pend; +end +assign cdcusbphy_inhandler_status_status1 = cdcusbphy_inhandler_done0; +assign cdcusbphy_inhandler_pending_status = cdcusbphy_inhandler_done1; +assign cdcusbphy_inhandler_done2 = cdcusbphy_inhandler_enable_storage; +assign cdcusbphy_outhandler_data_status[7:0] = cdcusbphy_outhandler_csrfield_data; +assign cdcusbphy_outhandler_csrfield_epno0 = cdcusbphy_outhandler_ctrl_storage[3:0]; +assign cdcusbphy_outhandler_csrfield_enable = cdcusbphy_outhandler_ctrl_storage[4]; +always @(*) begin + cdcusbphy_outhandler_csrfield_reset <= 1'd0; + if (cdcusbphy_outhandler_ctrl_re) begin + cdcusbphy_outhandler_csrfield_reset <= cdcusbphy_outhandler_ctrl_storage[5]; + end +end +assign cdcusbphy_outhandler_csrfield_stall = cdcusbphy_outhandler_ctrl_storage[6]; +always @(*) begin + cdcusbphy_outhandler_status_status0 <= 6'd0; + cdcusbphy_outhandler_status_status0[3:0] <= cdcusbphy_outhandler_csrfield_epno1; + cdcusbphy_outhandler_status_status0[4] <= cdcusbphy_outhandler_csrfield_have; + cdcusbphy_outhandler_status_status0[5] <= cdcusbphy_outhandler_csrfield_pend; +end +assign cdcusbphy_outhandler_status_status1 = cdcusbphy_outhandler_done0; +assign cdcusbphy_outhandler_pending_status = cdcusbphy_outhandler_done1; +assign cdcusbphy_outhandler_done2 = cdcusbphy_outhandler_enable_storage; +assign cdcusbphy_debug_packet_detected = (~cdcusbphy_debug_bridge_n_debug_in_progress); +assign cdcusbphy_address_reset = cdcusbphy_usb_core_usb_reset; +assign cdcusbphy_setuphandler_usb_reset = cdcusbphy_usb_core_usb_reset; +always @(*) begin + cdcusbphy_csrfield_setup <= 1'd0; + cdcusbphy_csrfield_reset <= 1'd0; + cdcusbphy_csrfield_in <= 1'd0; + cdcusbphy_csrfield_out <= 1'd0; + if (cdcusbphy_setuphandler_reset_pending) begin + cdcusbphy_csrfield_reset <= 1'd1; + end else begin + if (cdcusbphy_in_next) begin + cdcusbphy_csrfield_in <= 1'd1; + end else begin + if (cdcusbphy_out_next) begin + cdcusbphy_csrfield_out <= cdcusbphy_out_next; + end else begin + if (cdcusbphy_setuphandler_packet_pending) begin + cdcusbphy_csrfield_setup <= 1'd1; + end + end + end + end +end +assign cdcusbphy_usb_core_dtb = (cdcusbphy_inhandler_dtb | cdcusbphy_debug_packet_detected); +assign cdcusbphy_resetinserter_reset = cdcusbphy_usb_core_usb_reset; +assign cdcusbphy_usb_core_reset0 = (cdcusbphy_usb_core_error | cdcusbphy_usb_core_reset1); +assign cdcusbphy_usb_core_tx_i_bit_strobe = cdcusbphy_usb_core_rx_o_bit_strobe; +assign cdcusbphy_usb_core_usb_reset = cdcusbphy_usb_core_rx_o_reset; +assign cdcusbphy_usb_core_rx_i_usbp = usb_iobuf_usb_p_rx; +assign cdcusbphy_usb_core_rx_i_usbn = usb_iobuf_usb_n_rx; +assign usb_iobuf_usb_tx_en = cdcusbphy_usb_core_tx_o_oe; +assign usb_iobuf_usb_p_tx = cdcusbphy_usb_core_tx_o_usbp; +assign usb_iobuf_usb_n_tx = cdcusbphy_usb_core_tx_o_usbn; +assign cdcusbphy_usb_core_end = (cdcusbphy_usb_core_commit | cdcusbphy_usb_core_abort); +assign cdcusbphy_usb_core_transfer_reset = cdcusbphy_usb_core_reset0; +assign cdcusbphy_usb_core_data_recv_payload = cdcusbphy_usb_core_rx_o_data_payload; +assign cdcusbphy_usb_core_txstate_i_data_payload0 = cdcusbphy_usb_core_data_send_payload; +assign cdcusbphy_usb_core_txstate_i_data_ready = cdcusbphy_usb_core_data_send_have; +always @(*) begin + cdcusbphy_usb_core_rx_reset0 <= 1'd0; + if (cdcusbphy_usb_core_tx_o_oe) begin + cdcusbphy_usb_core_rx_reset0 <= 1'd1; + end +end +assign usb_pullup = usb_iobuf_usb_pullup; +always @(*) begin + usb_iobuf_usb_n_rx <= 1'd0; + usb_iobuf_usb_p_rx <= 1'd0; + if (usb_iobuf_usb_tx_en) begin + usb_iobuf_usb_p_rx <= 1'd1; + usb_iobuf_usb_n_rx <= 1'd0; + end else begin + usb_iobuf_usb_p_rx <= usb_iobuf_usb_p_t_i; + usb_iobuf_usb_n_rx <= usb_iobuf_usb_n_t_i; + end +end +assign cdcusbphy_usb_core_tx_shifter_i_data = cdcusbphy_usb_core_tx_i_data_payload; +assign cdcusbphy_usb_core_tx_shifter_reset = (cdcusbphy_usb_core_tx_da_reset_shifter | cdcusbphy_usb_core_tx_sp_reset_shifter); +assign cdcusbphy_usb_core_tx_shifter_ce = (~cdcusbphy_usb_core_tx_stall); +assign cdcusbphy_usb_core_tx_bitstuff_reset = cdcusbphy_usb_core_tx_da_reset_bitstuff; +assign cdcusbphy_usb_core_tx_bitstuff_i_data = cdcusbphy_usb_core_tx_shifter_o_data; +assign cdcusbphy_usb_core_tx_stall = cdcusbphy_usb_core_tx_bitstuff_o_stall; +assign cdcusbphy_usb_core_tx_sp_bit = cdcusbphy_usb_core_tx_sync_pulse[0]; +assign cdcusbphy_usb_core_tx_sp_reset_bitstuff = cdcusbphy_usb_core_tx_sync_pulse[0]; +assign cdcusbphy_usb_core_tx_sp_reset_shifter = cdcusbphy_usb_core_tx_sync_pulse[1]; +assign cdcusbphy_usb_core_tx_sp_o_data_strobe = cdcusbphy_usb_core_tx_sync_pulse[5]; +assign cdcusbphy_usb_core_tx_state_data = (cdcusbphy_usb_core_tx_state_gray[0] & cdcusbphy_usb_core_tx_state_gray[1]); +assign cdcusbphy_usb_core_tx_state_sync = (cdcusbphy_usb_core_tx_state_gray[0] & (~cdcusbphy_usb_core_tx_state_gray[1])); +assign cdcusbphy_usb_core_tx_fit_oe = (cdcusbphy_usb_core_tx_state_data | cdcusbphy_usb_core_tx_state_sync); +assign cdcusbphy_usb_core_tx_fit_dat = (((cdcusbphy_usb_core_tx_state_data & cdcusbphy_usb_core_tx_shifter_o_data) & (~cdcusbphy_usb_core_tx_bitstuff_o_stall)) | cdcusbphy_usb_core_tx_sp_bit); +assign cdcusbphy_usb_core_tx_o_data_strobe = ((((cdcusbphy_usb_core_tx_state_data & cdcusbphy_usb_core_tx_shifter_o_get) & (~cdcusbphy_usb_core_tx_stall)) & cdcusbphy_usb_core_tx_i_oe) | cdcusbphy_usb_core_tx_sp_o_data_strobe); +assign cdcusbphy_usb_core_tx_nrzi_i_valid = cdcusbphy_usb_core_tx_i_bit_strobe; +assign cdcusbphy_usb_core_tx_nrzi_i_data = cdcusbphy_usb_core_tx_nrzi_dat; +assign cdcusbphy_usb_core_tx_nrzi_i_oe = cdcusbphy_usb_core_tx_nrzi_oe1; +assign cdcusbphy_usb_core_tx_o_usbp = cdcusbphy_usb_core_tx_nrzi_o_usbp; +assign cdcusbphy_usb_core_tx_o_usbn = cdcusbphy_usb_core_tx_nrzi_o_usbn; +assign cdcusbphy_usb_core_tx_o_oe = cdcusbphy_usb_core_tx_nrzi_o_oe; +always @(*) begin + subfragments_fsm_next_state <= 2'd0; + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= 8'd0; + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd0; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd0; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd0; + subfragments_fsm_next_state <= subfragments_fsm_state; + case (subfragments_fsm_state) + 1'd1: begin + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= (cdcusbphy_usb_core_tx_sync_pulse >>> 1'd1); + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd1; + if (cdcusbphy_usb_core_tx_sync_pulse[0]) begin + subfragments_fsm_next_state <= 2'd2; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd3; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + end else begin + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd1; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + end + end + 2'd2: begin + if ((((~cdcusbphy_usb_core_tx_i_oe) & cdcusbphy_usb_core_tx_shifter_o_empty) & (~cdcusbphy_usb_core_tx_bitstuff_o_stall))) begin + if (cdcusbphy_usb_core_tx_bitstuff_o_will_stall) begin + subfragments_fsm_next_state <= 2'd3; + end else begin + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd2; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + subfragments_fsm_next_state <= 1'd0; + end + end else begin + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd3; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + end + end + 2'd3: begin + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 2'd2; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + subfragments_fsm_next_state <= 1'd0; + end + default: begin + if (cdcusbphy_usb_core_tx_i_oe) begin + subfragments_fsm_next_state <= 1'd1; + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0 <= 8'd128; + cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0 <= 1'd1; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd1; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + end else begin + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1 <= 1'd0; + cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1 <= 1'd1; + end + end + endcase +end +assign cdcusbphy_usb_core_tx_shifter_empty = cdcusbphy_usb_core_tx_shifter_pos[0]; +assign cdcusbphy_usb_core_tx_shifter_o_empty = cdcusbphy_usb_core_tx_shifter_empty; +assign cdcusbphy_usb_core_tx_shifter_o_data = cdcusbphy_usb_core_tx_shifter_shifter[0]; +assign cdcusbphy_usb_core_tx_bitstuff_o_stall = cdcusbphy_usb_core_tx_bitstuff_stuff_bit; +always @(*) begin + cdcusbphy_usb_core_tx_bitstuff_o_will_stall <= 1'd0; + subfragments_resetinserter_next_state <= 3'd0; + cdcusbphy_usb_core_tx_bitstuff_stuff_bit <= 1'd0; + subfragments_resetinserter_next_state <= subfragments_resetinserter_state; + case (subfragments_resetinserter_state) + 1'd1: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + subfragments_resetinserter_next_state <= 2'd2; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + 2'd2: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + subfragments_resetinserter_next_state <= 2'd3; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + 2'd3: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + subfragments_resetinserter_next_state <= 3'd4; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + 3'd4: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + subfragments_resetinserter_next_state <= 3'd5; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + 3'd5: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + cdcusbphy_usb_core_tx_bitstuff_o_will_stall <= 1'd1; + subfragments_resetinserter_next_state <= 3'd6; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + 3'd6: begin + cdcusbphy_usb_core_tx_bitstuff_stuff_bit <= 1'd1; + subfragments_resetinserter_next_state <= 1'd0; + end + default: begin + if (cdcusbphy_usb_core_tx_bitstuff_i_data) begin + subfragments_resetinserter_next_state <= 1'd1; + end else begin + subfragments_resetinserter_next_state <= 1'd0; + end + end + endcase +end +always @(*) begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + subfragments_txnrziencoder_next_state <= 3'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd0; + subfragments_txnrziencoder_next_state <= subfragments_txnrziencoder_state; + case (subfragments_txnrziencoder_state) + 1'd1: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + if ((~cdcusbphy_usb_core_tx_nrzi_i_oe)) begin + subfragments_txnrziencoder_next_state <= 2'd3; + end else begin + if (cdcusbphy_usb_core_tx_nrzi_i_data) begin + subfragments_txnrziencoder_next_state <= 1'd1; + end else begin + subfragments_txnrziencoder_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd1; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + if ((~cdcusbphy_usb_core_tx_nrzi_i_oe)) begin + subfragments_txnrziencoder_next_state <= 2'd3; + end else begin + if (cdcusbphy_usb_core_tx_nrzi_i_data) begin + subfragments_txnrziencoder_next_state <= 2'd2; + end else begin + subfragments_txnrziencoder_next_state <= 1'd1; + end + end + end + end + 2'd3: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + subfragments_txnrziencoder_next_state <= 3'd4; + end + end + 3'd4: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + subfragments_txnrziencoder_next_state <= 3'd5; + end + end + 3'd5: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd1; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + subfragments_txnrziencoder_next_state <= 1'd0; + end + end + default: begin + cdcusbphy_usb_core_tx_nrzi_usbp <= 1'd1; + cdcusbphy_usb_core_tx_nrzi_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_oe0 <= 1'd0; + if (cdcusbphy_usb_core_tx_nrzi_i_valid) begin + if (cdcusbphy_usb_core_tx_nrzi_i_oe) begin + subfragments_txnrziencoder_next_state <= 2'd2; + end + end + end + endcase +end +assign cdcusbphy_usb_core_txstate_i_data_payload1 = cdcusbphy_usb_core_txstate_i_data_payload0; +assign cdcusbphy_usb_core_txstate_reset = cdcusbphy_usb_core_txstate_is_ongoing0; +always @(*) begin + cdcusbphy_usb_core_txstate_i_data_strobe <= 1'd0; + if (cdcusbphy_usb_core_txstate_is_ongoing1) begin + cdcusbphy_usb_core_txstate_i_data_strobe <= cdcusbphy_usb_core_tx_o_data_strobe; + end +end +always @(*) begin + cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 <= 1'd0; + cdcusbphy_usb_core_txstate_is_ongoing1 <= 1'd0; + cdcusbphy_usb_core_txstate_is_ongoing0 <= 1'd0; + cdcusbphy_usb_core_tx_i_data_payload <= 8'd0; + cdcusbphy_usb_core_txstate_o_pkt_end <= 1'd0; + subfragments_txpacketsend_next_state <= 4'd0; + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0; + cdcusbphy_usb_core_txstate_o_data_ack <= 1'd0; + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd0; + cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 <= 4'd0; + subfragments_txpacketsend_next_state <= subfragments_txpacketsend_state; + case (subfragments_txpacketsend_state) + 1'd1: begin + cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1 <= cdcusbphy_usb_core_txstate_i_pid; + cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1 <= 1'd1; + cdcusbphy_usb_core_tx_i_data_payload <= 1'd1; + if (cdcusbphy_usb_core_tx_o_data_strobe) begin + subfragments_txpacketsend_next_state <= 2'd2; + end + end + 2'd2: begin + cdcusbphy_usb_core_tx_i_data_payload <= {(cdcusbphy_usb_core_txstate_pid ^ 4'd15), cdcusbphy_usb_core_txstate_pid}; + if (cdcusbphy_usb_core_tx_o_data_strobe) begin + if (((cdcusbphy_usb_core_txstate_pid & 2'd3) == 2'd2)) begin + subfragments_txpacketsend_next_state <= 3'd7; + end else begin + if (((cdcusbphy_usb_core_txstate_pid & 2'd3) == 2'd3)) begin + subfragments_txpacketsend_next_state <= 2'd3; + end else begin + subfragments_txpacketsend_next_state <= 4'd8; + end + end + end + cdcusbphy_usb_core_txstate_is_ongoing0 <= 1'd1; + end + 2'd3: begin + if ((~cdcusbphy_usb_core_txstate_i_data_ready)) begin + subfragments_txpacketsend_next_state <= 3'd5; + end else begin + subfragments_txpacketsend_next_state <= 3'd4; + end + end + 3'd4: begin + cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_i_data_payload0; + cdcusbphy_usb_core_txstate_o_data_ack <= cdcusbphy_usb_core_tx_o_data_strobe; + if ((~cdcusbphy_usb_core_txstate_i_data_ready)) begin + subfragments_txpacketsend_next_state <= 3'd5; + end + cdcusbphy_usb_core_txstate_is_ongoing1 <= 1'd1; + end + 3'd5: begin + cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_o_crc[7:0]; + if (cdcusbphy_usb_core_tx_o_data_strobe) begin + subfragments_txpacketsend_next_state <= 3'd6; + end + end + 3'd6: begin + cdcusbphy_usb_core_tx_i_data_payload <= cdcusbphy_usb_core_txstate_o_crc[15:8]; + if (cdcusbphy_usb_core_tx_o_data_strobe) begin + subfragments_txpacketsend_next_state <= 3'd7; + end + end + 3'd7: begin + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0; + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1; + if ((~cdcusbphy_usb_core_txstate_o_oe12)) begin + cdcusbphy_usb_core_txstate_o_pkt_end <= 1'd1; + subfragments_txpacketsend_next_state <= 1'd0; + end + end + default: begin + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= cdcusbphy_usb_core_txstate_i_pkt_start; + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1; + if (cdcusbphy_usb_core_txstate_i_pkt_start) begin + subfragments_txpacketsend_next_state <= 1'd1; + end else begin + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0 <= 1'd0; + cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0 <= 1'd1; + end + end + endcase +end +assign cdcusbphy_usb_core_txstate_crc_dat = {cdcusbphy_usb_core_txstate_i_data_payload1[0], cdcusbphy_usb_core_txstate_i_data_payload1[1], cdcusbphy_usb_core_txstate_i_data_payload1[2], cdcusbphy_usb_core_txstate_i_data_payload1[3], cdcusbphy_usb_core_txstate_i_data_payload1[4], cdcusbphy_usb_core_txstate_i_data_payload1[5], cdcusbphy_usb_core_txstate_i_data_payload1[6], cdcusbphy_usb_core_txstate_i_data_payload1[7]}; +assign cdcusbphy_usb_core_txstate_o_crc = ({cdcusbphy_usb_core_txstate_crc_cur[0], cdcusbphy_usb_core_txstate_crc_cur[1], cdcusbphy_usb_core_txstate_crc_cur[2], cdcusbphy_usb_core_txstate_crc_cur[3], cdcusbphy_usb_core_txstate_crc_cur[4], cdcusbphy_usb_core_txstate_crc_cur[5], cdcusbphy_usb_core_txstate_crc_cur[6], cdcusbphy_usb_core_txstate_crc_cur[7], cdcusbphy_usb_core_txstate_crc_cur[8], cdcusbphy_usb_core_txstate_crc_cur[9], cdcusbphy_usb_core_txstate_crc_cur[10], cdcusbphy_usb_core_txstate_crc_cur[11], cdcusbphy_usb_core_txstate_crc_cur[12], cdcusbphy_usb_core_txstate_crc_cur[13], cdcusbphy_usb_core_txstate_crc_cur[14], cdcusbphy_usb_core_txstate_crc_cur[15]} ^ 16'd65535); +always @(*) begin + cdcusbphy_usb_core_txstate_crc_next <= 16'd64770; + cdcusbphy_usb_core_txstate_crc_next[0] <= (((((((((((((((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]); + cdcusbphy_usb_core_txstate_crc_next[1] <= (((((((((((((cdcusbphy_usb_core_txstate_crc_dat[1] ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]); + cdcusbphy_usb_core_txstate_crc_next[2] <= (((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]); + cdcusbphy_usb_core_txstate_crc_next[3] <= (((cdcusbphy_usb_core_txstate_crc_dat[1] ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]); + cdcusbphy_usb_core_txstate_crc_next[4] <= (((cdcusbphy_usb_core_txstate_crc_dat[2] ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]); + cdcusbphy_usb_core_txstate_crc_next[5] <= (((cdcusbphy_usb_core_txstate_crc_dat[3] ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]); + cdcusbphy_usb_core_txstate_crc_next[6] <= (((cdcusbphy_usb_core_txstate_crc_dat[4] ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]); + cdcusbphy_usb_core_txstate_crc_next[7] <= (((cdcusbphy_usb_core_txstate_crc_dat[5] ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]); + cdcusbphy_usb_core_txstate_crc_next[8] <= ((((cdcusbphy_usb_core_txstate_crc_dat[6] ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[0]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]); + cdcusbphy_usb_core_txstate_crc_next[9] <= ((cdcusbphy_usb_core_txstate_crc_dat[7] ^ cdcusbphy_usb_core_txstate_crc_cur[1]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]); + cdcusbphy_usb_core_txstate_crc_next[10] <= cdcusbphy_usb_core_txstate_crc_cur[2]; + cdcusbphy_usb_core_txstate_crc_next[11] <= cdcusbphy_usb_core_txstate_crc_cur[3]; + cdcusbphy_usb_core_txstate_crc_next[12] <= cdcusbphy_usb_core_txstate_crc_cur[4]; + cdcusbphy_usb_core_txstate_crc_next[13] <= cdcusbphy_usb_core_txstate_crc_cur[5]; + cdcusbphy_usb_core_txstate_crc_next[14] <= cdcusbphy_usb_core_txstate_crc_cur[6]; + cdcusbphy_usb_core_txstate_crc_next[15] <= ((((((((((((((((cdcusbphy_usb_core_txstate_crc_dat[0] ^ cdcusbphy_usb_core_txstate_crc_dat[1]) ^ cdcusbphy_usb_core_txstate_crc_dat[2]) ^ cdcusbphy_usb_core_txstate_crc_dat[3]) ^ cdcusbphy_usb_core_txstate_crc_dat[4]) ^ cdcusbphy_usb_core_txstate_crc_dat[5]) ^ cdcusbphy_usb_core_txstate_crc_dat[6]) ^ cdcusbphy_usb_core_txstate_crc_dat[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[7]) ^ cdcusbphy_usb_core_txstate_crc_cur[8]) ^ cdcusbphy_usb_core_txstate_crc_cur[9]) ^ cdcusbphy_usb_core_txstate_crc_cur[10]) ^ cdcusbphy_usb_core_txstate_crc_cur[11]) ^ cdcusbphy_usb_core_txstate_crc_cur[12]) ^ cdcusbphy_usb_core_txstate_crc_cur[13]) ^ cdcusbphy_usb_core_txstate_crc_cur[14]) ^ cdcusbphy_usb_core_txstate_crc_cur[15]); +end +assign cdcusbphy_usb_core_rx_o_bit_strobe = cdcusbphy_usb_core_rx_line_state_valid; +assign cdcusbphy_usb_core_rx_o_reset = cdcusbphy_usb_core_rx_reset_counter[6]; +assign cdcusbphy_usb_core_rx_nrzi_i_valid = cdcusbphy_usb_core_rx_o_bit_strobe; +assign cdcusbphy_usb_core_rx_nrzi_i_dj = cdcusbphy_usb_core_rx_line_state_dj1; +assign cdcusbphy_usb_core_rx_nrzi_i_dk = cdcusbphy_usb_core_rx_line_state_dk1; +assign cdcusbphy_usb_core_rx_nrzi_i_se0 = cdcusbphy_usb_core_rx_line_state_se01; +assign cdcusbphy_usb_core_rx_detect_reset = cdcusbphy_usb_core_rx_reset0; +assign cdcusbphy_usb_core_rx_detect_i_valid = cdcusbphy_usb_core_rx_nrzi_o_valid; +assign cdcusbphy_usb_core_rx_detect_i_se0 = cdcusbphy_usb_core_rx_nrzi_o_se0; +assign cdcusbphy_usb_core_rx_detect_i_data = cdcusbphy_usb_core_rx_nrzi_o_data; +assign cdcusbphy_usb_core_rx_reset1 = (~cdcusbphy_usb_core_rx_detect_o_pkt_active); +assign cdcusbphy_usb_core_rx_bitstuff_reset = ((~cdcusbphy_usb_core_rx_detect_o_pkt_active) | cdcusbphy_usb_core_rx_reset0); +assign cdcusbphy_usb_core_rx_bitstuff_i_valid = cdcusbphy_usb_core_rx_nrzi_o_valid; +assign cdcusbphy_usb_core_rx_bitstuff_i_data = cdcusbphy_usb_core_rx_nrzi_o_data; +assign cdcusbphy_usb_core_rx_shifter_reset = cdcusbphy_usb_core_rx_last_reset; +assign cdcusbphy_usb_core_rx_shifter_i_data = cdcusbphy_usb_core_rx_bitstuff_o_data; +assign cdcusbphy_usb_core_rx_shifter_i_valid = ((~cdcusbphy_usb_core_rx_bitstuff_o_stall) & cdcusbphy_usb_core_rx_detect_o_pkt_active); +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din = {cdcusbphy_usb_core_rx_shifter_o_data[0], cdcusbphy_usb_core_rx_shifter_o_data[1], cdcusbphy_usb_core_rx_shifter_o_data[2], cdcusbphy_usb_core_rx_shifter_o_data[3], cdcusbphy_usb_core_rx_shifter_o_data[4], cdcusbphy_usb_core_rx_shifter_o_data[5], cdcusbphy_usb_core_rx_shifter_o_data[6], cdcusbphy_usb_core_rx_shifter_o_data[7]}; +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we = cdcusbphy_usb_core_rx_shifter_o_put; +assign cdcusbphy_usb_core_rx_o_data_payload = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout; +assign cdcusbphy_usb_core_rx_o_data_strobe = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable; +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re = 1'd1; +always @(*) begin + cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din <= 2'd0; + cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din[1] <= cdcusbphy_usb_core_rx_detect_o_pkt_start; + cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din[0] <= cdcusbphy_usb_core_rx_detect_o_pkt_end; +end +assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we = (cdcusbphy_usb_core_rx_detect_o_pkt_start | cdcusbphy_usb_core_rx_detect_o_pkt_end); +assign cdcusbphy_usb_core_rx_flag_start = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout[1]; +assign cdcusbphy_usb_core_rx_flag_end = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout[0]; +assign cdcusbphy_usb_core_rx_flag_valid = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable; +assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re = 1'd1; +assign cdcusbphy_usb_core_rx_o_pkt_start = (cdcusbphy_usb_core_rx_flag_start & cdcusbphy_usb_core_rx_flag_valid); +assign cdcusbphy_usb_core_rx_o_pkt_end = (cdcusbphy_usb_core_rx_flag_end & cdcusbphy_usb_core_rx_flag_valid); +assign cdcusbphy_usb_core_rx_dpair = {cdcusbphy_usb_core_rx_i_usbp, cdcusbphy_usb_core_rx_i_usbn}; +always @(*) begin + cdcusbphy_usb_core_rx_line_state_dj0 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_dk0 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_se00 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_se10 <= 1'd0; + subfragments_rxpipeline_next_state <= 3'd0; + cdcusbphy_usb_core_rx_line_state_dt <= 1'd0; + subfragments_rxpipeline_next_state <= subfragments_rxpipeline_state; + case (subfragments_rxpipeline_state) + 1'd1: begin + cdcusbphy_usb_core_rx_line_state_dj0 <= 1'd1; + if ((cdcusbphy_usb_core_rx_dpair != 2'd2)) begin + subfragments_rxpipeline_next_state <= 1'd0; + end + end + 2'd2: begin + cdcusbphy_usb_core_rx_line_state_dk0 <= 1'd1; + if ((cdcusbphy_usb_core_rx_dpair != 1'd1)) begin + subfragments_rxpipeline_next_state <= 1'd0; + end + end + 2'd3: begin + cdcusbphy_usb_core_rx_line_state_se00 <= 1'd1; + if ((cdcusbphy_usb_core_rx_dpair != 1'd0)) begin + subfragments_rxpipeline_next_state <= 1'd0; + end + end + 3'd4: begin + cdcusbphy_usb_core_rx_line_state_se10 <= 1'd1; + if ((cdcusbphy_usb_core_rx_dpair != 2'd3)) begin + subfragments_rxpipeline_next_state <= 1'd0; + end + end + default: begin + cdcusbphy_usb_core_rx_line_state_dt <= 1'd1; + case (cdcusbphy_usb_core_rx_dpair) + 1'd0: begin + subfragments_rxpipeline_next_state <= 2'd3; + end + 1'd1: begin + subfragments_rxpipeline_next_state <= 2'd2; + end + 2'd2: begin + subfragments_rxpipeline_next_state <= 1'd1; + end + 2'd3: begin + subfragments_rxpipeline_next_state <= 3'd4; + end + endcase + end + endcase +end +assign cdcusbphy_usb_core_rx_detect_o_pkt_start = cdcusbphy_usb_core_rx_detect_pkt_start; +assign cdcusbphy_usb_core_rx_detect_o_pkt_active = cdcusbphy_usb_core_rx_detect_pkt_active; +assign cdcusbphy_usb_core_rx_detect_o_pkt_end = cdcusbphy_usb_core_rx_detect_pkt_end; +always @(*) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd0; + cdcusbphy_usb_core_rx_detect_pkt_start <= 1'd0; + cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd0; + cdcusbphy_usb_core_rx_detect_pkt_end <= 1'd0; + subfragments_rxpipeline_rxpacketdetect_next_state <= subfragments_rxpipeline_rxpacketdetect_state; + case (subfragments_rxpipeline_rxpacketdetect_state) + 1'd1: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 2'd2; + end + end + end + 2'd2: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 2'd3; + end + end + end + 2'd3: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd4; + end + end + end + 3'd4: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd5; + end + end + end + 3'd5: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if (cdcusbphy_usb_core_rx_detect_i_se0) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + if (cdcusbphy_usb_core_rx_detect_i_data) begin + cdcusbphy_usb_core_rx_detect_pkt_start <= 1'd1; + subfragments_rxpipeline_rxpacketdetect_next_state <= 3'd6; + end + end + end + end + 3'd6: begin + cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd1; + if ((cdcusbphy_usb_core_rx_detect_i_valid & cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + cdcusbphy_usb_core_rx_detect_pkt_active <= 1'd0; + cdcusbphy_usb_core_rx_detect_pkt_end <= 1'd1; + end + end + default: begin + if (cdcusbphy_usb_core_rx_detect_i_valid) begin + if ((cdcusbphy_usb_core_rx_detect_i_data | cdcusbphy_usb_core_rx_detect_i_se0)) begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd0; + end else begin + subfragments_rxpipeline_rxpacketdetect_next_state <= 1'd1; + end + end + end + endcase +end +always @(*) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd0; + cdcusbphy_usb_core_rx_bitstuff_drop_bit <= 1'd0; + subfragments_rxpipeline_rxbitstuffremover_next_state <= subfragments_rxpipeline_rxbitstuffremover_state; + case (subfragments_rxpipeline_rxbitstuffremover_state) + 1'd1: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 2'd2; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + 2'd2: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 2'd3; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + 2'd3: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd4; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + 3'd4: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd5; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + 3'd5: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 3'd6; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + 3'd6: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + cdcusbphy_usb_core_rx_bitstuff_drop_bit <= 1'd1; + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + default: begin + if (cdcusbphy_usb_core_rx_bitstuff_i_valid) begin + if (cdcusbphy_usb_core_rx_bitstuff_i_data) begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd1; + end else begin + subfragments_rxpipeline_rxbitstuffremover_next_state <= 1'd0; + end + end + end + endcase +end +assign cdcusbphy_usb_core_rx_shifter_o_data = cdcusbphy_usb_core_rx_shifter_shift_reg[7:0]; +assign cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce = (cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable & cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_we); +assign cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce = (cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable & cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_re); +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_writable = ((cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q[1] == cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain[1]) | (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q[0] == cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain[0])); +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_readable = (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q != cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain); +assign cdcusbphy_usb_core_rx_payloadFifo_wrport_adr = cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary[0]; +assign cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w = cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_din; +assign cdcusbphy_usb_core_rx_payloadFifo_wrport_we = cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce; +assign cdcusbphy_usb_core_rx_payloadFifo_rdport_adr = cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary[0]; +assign cdcusbphy_usb_core_rx_payloadFifo_asyncfifo_dout = cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r; +always @(*) begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= 2'd0; + if (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_ce) begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary + 1'd1); + end else begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary; + end +end +assign cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next = (cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary ^ cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary[1]); +always @(*) begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= 2'd0; + if (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_ce) begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary + 1'd1); + end else begin + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary; + end +end +assign cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next = (cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary ^ cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary[1]); +assign cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce = (cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable & cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_we); +assign cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce = (cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable & cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_re); +assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_writable = ((cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q[1] == cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain[1]) | (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q[0] == cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain[0])); +assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_readable = (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q != cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain); +assign cdcusbphy_usb_core_rx_flagsFifo_wrport_adr = cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary[0]; +assign cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w = cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_din; +assign cdcusbphy_usb_core_rx_flagsFifo_wrport_we = cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce; +assign cdcusbphy_usb_core_rx_flagsFifo_rdport_adr = cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary[0]; +assign cdcusbphy_usb_core_rx_flagsFifo_asyncfifo_dout = cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r; +always @(*) begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= 2'd0; + if (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_ce) begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary + 1'd1); + end else begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary; + end +end +assign cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next = (cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary ^ cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary[1]); +always @(*) begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= 2'd0; + if (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_ce) begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary + 1'd1); + end else begin + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary; + end +end +assign cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next = (cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary ^ cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary[1]); +always @(*) begin + cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 <= 1'd0; + subfragments_packetheaderdecode_next_value <= 7'd0; + subfragments_packetheaderdecode_next_value_ce <= 1'd0; + cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 <= 1'd0; + cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 <= 1'd0; + cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 <= 4'd0; + cdcusbphy_usb_core_o_decoded <= 1'd0; + cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 <= 1'd0; + cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 <= 5'd0; + cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 <= 1'd0; + subfragments_packetheaderdecode_next_state <= 3'd0; + cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 <= 4'd0; + subfragments_packetheaderdecode_next_state <= subfragments_packetheaderdecode_state; + case (subfragments_packetheaderdecode_state) + 1'd1: begin + if (cdcusbphy_usb_core_rx_o_data_strobe) begin + cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0 <= cdcusbphy_usb_core_rx_o_data_payload[3:0]; + cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0 <= 1'd1; + case ((cdcusbphy_usb_core_rx_o_data_payload[3:0] & 2'd3)) + 1'd1: begin + subfragments_packetheaderdecode_next_state <= 2'd2; + end + 2'd2: begin + subfragments_packetheaderdecode_next_state <= 3'd4; + end + 2'd3: begin + subfragments_packetheaderdecode_next_state <= 3'd4; + end + endcase + end + end + 2'd2: begin + if (cdcusbphy_usb_core_rx_o_data_strobe) begin + subfragments_packetheaderdecode_next_value <= cdcusbphy_usb_core_rx_o_data_payload[6:0]; + subfragments_packetheaderdecode_next_value_ce <= 1'd1; + cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1 <= cdcusbphy_usb_core_rx_o_data_payload[7]; + cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1 <= 1'd1; + subfragments_packetheaderdecode_next_state <= 2'd3; + end + end + 2'd3: begin + if (cdcusbphy_usb_core_rx_o_data_strobe) begin + cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2 <= {cdcusbphy_usb_core_rx_o_data_payload[2:0], cdcusbphy_usb_core_endp4}; + cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2 <= 1'd1; + cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3 <= cdcusbphy_usb_core_rx_o_data_payload[7:4]; + cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3 <= 1'd1; + subfragments_packetheaderdecode_next_state <= 3'd4; + end + end + 3'd4: begin + cdcusbphy_usb_core_o_decoded <= 1'd1; + subfragments_packetheaderdecode_next_state <= 1'd0; + end + default: begin + if (cdcusbphy_usb_core_rx_o_pkt_start) begin + subfragments_packetheaderdecode_next_state <= 1'd1; + end + end + endcase +end +assign cdcusbphy_usb_core_is_el0 = ((~(subfragments_clockdomainsrenamer_state0 == 3'd6)) & (subfragments_clockdomainsrenamer_next_state0 == 3'd6)); +assign cdcusbphy_usb_core_is_el1 = ((~(subfragments_clockdomainsrenamer_state0 == 4'd8)) & (subfragments_clockdomainsrenamer_next_state0 == 4'd8)); +always @(*) begin + cdcusbphy_usb_core_data_recv_put <= 1'd0; + subfragments_clockdomainsrenamer_next_state0 <= 4'd0; + cdcusbphy_usb_core_data_send_get <= 1'd0; + cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd0; + cdcusbphy_usb_core_txstate_i_pid <= 4'd0; + cdcusbphy_usb_core_tok_csrtransform_f_next_value0 <= 4'd0; + cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 <= 1'd0; + cdcusbphy_usb_core_idle <= 1'd0; + cdcusbphy_usb_core_endp_csrtransform_f_next_value1 <= 4'd0; + cdcusbphy_usb_core_start <= 1'd0; + cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 <= 1'd0; + cdcusbphy_usb_core_poll <= 1'd0; + cdcusbphy_usb_core_setup <= 1'd0; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd0; + cdcusbphy_usb_core_commit <= 1'd0; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd0; + cdcusbphy_usb_core_retry <= 1'd0; + cdcusbphy_usb_core_abort <= 1'd0; + cdcusbphy_usb_core_data_end <= 1'd0; + cdcusbphy_usb_core_error <= 1'd0; + if (cdcusbphy_usb_core_is_el0) begin + if (cdcusbphy_usb_core_dtb) begin + cdcusbphy_usb_core_txstate_i_pid <= 4'd11; + end else begin + cdcusbphy_usb_core_txstate_i_pid <= 2'd3; + end + cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd1; + end + if (cdcusbphy_usb_core_is_el1) begin + cdcusbphy_usb_core_txstate_i_pid <= cdcusbphy_usb_core_response_pid; + cdcusbphy_usb_core_txstate_i_pkt_start <= 1'd1; + end + subfragments_clockdomainsrenamer_next_state0 <= subfragments_clockdomainsrenamer_state0; + case (subfragments_clockdomainsrenamer_state0) + 1'd0: begin + cdcusbphy_usb_core_error <= 1'd1; + end + 2'd2: begin + cdcusbphy_usb_core_idle <= 1'd0; + if (cdcusbphy_usb_core_o_decoded) begin + if ((cdcusbphy_usb_core_o_addr != cdcusbphy_usb_core_addr)) begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd1; + end else begin + cdcusbphy_usb_core_start <= 1'd1; + cdcusbphy_usb_core_tok_csrtransform_f_next_value0 <= cdcusbphy_usb_core_o_pid; + cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0 <= 1'd1; + cdcusbphy_usb_core_endp_csrtransform_f_next_value1 <= cdcusbphy_usb_core_o_endp; + cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1 <= 1'd1; + subfragments_clockdomainsrenamer_next_state0 <= 2'd3; + end + end + end + 2'd3: begin + cdcusbphy_usb_core_poll <= 1'd1; + if (cdcusbphy_usb_core_rdy) begin + if ((cdcusbphy_usb_core_tok == 4'd13)) begin + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 2'd2; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1; + end else begin + if (cdcusbphy_usb_core_sta) begin + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd14; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1; + end else begin + if (cdcusbphy_usb_core_arm) begin + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 2'd2; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1; + end else begin + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value <= 4'd10; + cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce <= 1'd1; + end + end + end + if ((cdcusbphy_usb_core_o_pid == 3'd5)) begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd1; + end else begin + if ((cdcusbphy_usb_core_tok == 4'd13)) begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd4; + end else begin + if ((cdcusbphy_usb_core_tok == 1'd1)) begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd4; + end else begin + if ((cdcusbphy_usb_core_tok == 4'd9)) begin + if (((~cdcusbphy_usb_core_arm) | cdcusbphy_usb_core_sta)) begin + subfragments_clockdomainsrenamer_next_state0 <= 4'd8; + end else begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd6; + end + end else begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd1; + end + end + end + end + end + end + 3'd4: begin + if (cdcusbphy_usb_core_o_decoded) begin + if (((cdcusbphy_usb_core_o_pid & 2'd3) == 2'd3)) begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd5; + end else begin + if ((cdcusbphy_usb_core_o_pid == 3'd5)) begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd4; + end else begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd0; + end + end + end + end + 3'd5: begin + if ((cdcusbphy_usb_core_response_pid == 2'd2)) begin + cdcusbphy_usb_core_data_recv_put <= cdcusbphy_usb_core_rx_o_data_strobe; + end + if (cdcusbphy_usb_core_rx_o_pkt_end) begin + subfragments_clockdomainsrenamer_next_state0 <= 4'd8; + end + end + 3'd6: begin + if (cdcusbphy_usb_core_dtb) begin + cdcusbphy_usb_core_txstate_i_pid <= 4'd11; + end else begin + cdcusbphy_usb_core_txstate_i_pid <= 2'd3; + end + cdcusbphy_usb_core_data_send_get <= cdcusbphy_usb_core_txstate_o_data_ack; + cdcusbphy_usb_core_data_end <= cdcusbphy_usb_core_txstate_o_pkt_end; + if (cdcusbphy_usb_core_txstate_o_pkt_end) begin + subfragments_clockdomainsrenamer_next_state0 <= 3'd7; + end + end + 3'd7: begin + if (cdcusbphy_usb_core_o_decoded) begin + cdcusbphy_usb_core_commit <= 1'd1; + if ((cdcusbphy_usb_core_o_pid == 2'd2)) begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd1; + end else begin + if ((cdcusbphy_usb_core_o_pid == 4'd9)) begin + cdcusbphy_usb_core_retry <= 1'd1; + subfragments_clockdomainsrenamer_next_state0 <= 3'd6; + end else begin + subfragments_clockdomainsrenamer_next_state0 <= 1'd0; + end + end + end + end + 4'd8: begin + cdcusbphy_usb_core_txstate_i_pid <= cdcusbphy_usb_core_response_pid; + if (cdcusbphy_usb_core_txstate_o_pkt_end) begin + cdcusbphy_usb_core_setup <= (cdcusbphy_usb_core_tok == 4'd13); + if ((cdcusbphy_usb_core_response_pid == 2'd2)) begin + cdcusbphy_usb_core_commit <= 1'd1; + end else begin + cdcusbphy_usb_core_abort <= 1'd1; + end + subfragments_clockdomainsrenamer_next_state0 <= 1'd1; + end + end + default: begin + cdcusbphy_usb_core_idle <= 1'd1; + if (cdcusbphy_usb_core_rx_o_pkt_start) begin + subfragments_clockdomainsrenamer_next_state0 <= 2'd2; + end + end + endcase +end +assign usb_iobuf_usb_pullup = cdcusbphy_pullup_storage; +always @(*) begin + cdcusbphy_debug_bridge_wishbone_cyc <= 1'd0; + cdcusbphy_debug_bridge_wishbone_stb <= 1'd0; + cdcusbphy_debug_bridge_wishbone_we <= 1'd0; + if ((cdcusbphy_debug_bridge_send_to_wishbone | cdcusbphy_debug_bridge_transfer_active)) begin + cdcusbphy_debug_bridge_wishbone_stb <= 1'd1; + cdcusbphy_debug_bridge_wishbone_we <= (~cdcusbphy_debug_bridge_cmd); + cdcusbphy_debug_bridge_wishbone_cyc <= 1'd1; + end +end +assign cdcusbphy_debug_bridge_reply_from_wishbone = (cdcusbphy_debug_bridge_wishbone_ack | cdcusbphy_debug_bridge_wishbone_err); +assign cdcusbphy_debug_bridge_wishbone_adr = cdcusbphy_debug_bridge_address[31:2]; +assign cdcusbphy_debug_bridge_wishbone_dat_w = cdcusbphy_debug_bridge_data; +assign cdcusbphy_debug_bridge_wishbone_sel = 4'd15; +always @(*) begin + cdcusbphy_debug_bridge_sink_data <= 8'd0; + case (cdcusbphy_debug_bridge_byte_counter) + 1'd0: begin + cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[7:0]; + end + 1'd1: begin + cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[15:8]; + end + 2'd2: begin + cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[23:16]; + end + default: begin + cdcusbphy_debug_bridge_sink_data <= cdcusbphy_debug_bridge_rd_data[31:24]; + end + endcase +end +always @(*) begin + cdcusbphy_debug_bridge_sink_valid <= 1'd0; + cdcusbphy_debug_bridge_send_ack <= 1'd0; + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1; + cdcusbphy_debug_bridge_byte_counter_reset <= 1'd0; + cdcusbphy_debug_bridge_address_ce <= 1'd0; + cdcusbphy_debug_bridge_byte_counter_ce <= 1'd0; + cdcusbphy_debug_bridge_rx_data_ce <= 1'd0; + cdcusbphy_debug_bridge_cmd_ce <= 1'd0; + cdcusbphy_debug_bridge_send_to_wishbone <= 1'd0; + cdcusbphy_debug_bridge_transfer_active <= 1'd0; + subfragments_usbwishbonebridge_next_state <= 4'd0; + subfragments_usbwishbonebridge_next_state <= subfragments_usbwishbonebridge_state; + case (subfragments_usbwishbonebridge_state) + 1'd1: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + if (cdcusbphy_usb_core_data_recv_put) begin + cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1; + if ((cdcusbphy_debug_bridge_byte_counter >= 1'd1)) begin + if ((cdcusbphy_debug_bridge_byte_counter <= 3'd4)) begin + cdcusbphy_debug_bridge_address_ce <= 1'd1; + end + end + end + if (cdcusbphy_usb_core_end) begin + cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1; + if (cdcusbphy_debug_bridge_cmd) begin + cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1; + subfragments_usbwishbonebridge_next_state <= 3'd5; + end else begin + subfragments_usbwishbonebridge_next_state <= 2'd2; + end + end + end + 2'd2: begin + cdcusbphy_debug_bridge_send_ack <= (cdcusbphy_usb_core_endp == 1'd0); + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + if ((cdcusbphy_usb_core_endp == 1'd0)) begin + if (cdcusbphy_usb_core_data_recv_put) begin + cdcusbphy_debug_bridge_rx_data_ce <= 1'd1; + cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1; + if ((cdcusbphy_debug_bridge_byte_counter == 2'd3)) begin + subfragments_usbwishbonebridge_next_state <= 2'd3; + end else begin + if (cdcusbphy_usb_core_end) begin + cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1; + subfragments_usbwishbonebridge_next_state <= 3'd4; + end + end + end + end + end + 2'd3: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + cdcusbphy_debug_bridge_send_ack <= 1'd1; + if (cdcusbphy_usb_core_end) begin + cdcusbphy_debug_bridge_send_to_wishbone <= 1'd1; + subfragments_usbwishbonebridge_next_state <= 3'd4; + end + end + 3'd4: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + cdcusbphy_debug_bridge_transfer_active <= 1'd1; + if (cdcusbphy_debug_bridge_reply_from_wishbone) begin + subfragments_usbwishbonebridge_next_state <= 4'd8; + end + end + 3'd5: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + cdcusbphy_debug_bridge_transfer_active <= 1'd1; + if (cdcusbphy_debug_bridge_reply_from_wishbone) begin + subfragments_usbwishbonebridge_next_state <= 3'd6; + end + end + 3'd6: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1; + if (cdcusbphy_usb_core_start) begin + subfragments_usbwishbonebridge_next_state <= 3'd7; + end + end + 3'd7: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + if ((cdcusbphy_usb_core_endp != 1'd0)) begin + subfragments_usbwishbonebridge_next_state <= 3'd6; + end + cdcusbphy_debug_bridge_sink_valid <= (cdcusbphy_usb_core_endp == 1'd0); + if (cdcusbphy_usb_core_data_send_get) begin + cdcusbphy_debug_bridge_byte_counter_ce <= 1'd1; + end + if ((cdcusbphy_debug_bridge_byte_counter == 3'd4)) begin + subfragments_usbwishbonebridge_next_state <= 4'd8; + end + if (cdcusbphy_usb_core_end) begin + subfragments_usbwishbonebridge_next_state <= 4'd8; + end + end + 4'd8: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + if (cdcusbphy_usb_core_start) begin + subfragments_usbwishbonebridge_next_state <= 4'd9; + end + end + 4'd9: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd0; + if ((cdcusbphy_usb_core_endp != 1'd0)) begin + subfragments_usbwishbonebridge_next_state <= 4'd8; + end + cdcusbphy_debug_bridge_send_ack <= (cdcusbphy_usb_core_endp == 1'd0); + if (cdcusbphy_usb_core_end) begin + subfragments_usbwishbonebridge_next_state <= 1'd0; + end + end + 4'd10: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1; + if (cdcusbphy_usb_core_end) begin + subfragments_usbwishbonebridge_next_state <= 1'd0; + end + end + default: begin + cdcusbphy_debug_bridge_n_debug_in_progress <= 1'd1; + if (cdcusbphy_usb_core_data_recv_put) begin + if ((cdcusbphy_usb_core_tok == 4'd13)) begin + if ((cdcusbphy_usb_core_endp == 1'd0)) begin + cdcusbphy_debug_bridge_cmd_ce <= 1'd1; + cdcusbphy_debug_bridge_byte_counter_reset <= 1'd1; + if ((cdcusbphy_usb_core_data_recv_payload[6:0] == 7'd67)) begin + subfragments_usbwishbonebridge_next_state <= 1'd1; + end else begin + subfragments_usbwishbonebridge_next_state <= 4'd10; + end + end + end + end + end + endcase +end +assign cdcusbphy_setuphandler_reset_trigger = (~cdcusbphy_setuphandler_usb_reset); +assign cdcusbphy_setuphandler_inner_reset = ((cdcusbphy_setuphandler_reset | cdcusbphy_setuphandler_begin) | cdcusbphy_setuphandler_csrfield_reset); +assign cdcusbphy_setuphandler_eventmanager_ready0 = cdcusbphy_setuphandler_packet_status; +assign cdcusbphy_setuphandler_eventmanager_ready1 = cdcusbphy_setuphandler_packet_pending; +always @(*) begin + cdcusbphy_setuphandler_packet_clear <= 1'd0; + cdcusbphy_setuphandler_packet_clear <= cdcusbphy_setuphandler_begin; + if ((cdcusbphy_setuphandler_eventmanager_pending_re & cdcusbphy_setuphandler_eventmanager_pending_r[0])) begin + cdcusbphy_setuphandler_packet_clear <= 1'd1; + end +end +assign cdcusbphy_setuphandler_eventmanager_reset0 = cdcusbphy_setuphandler_reset_status; +assign cdcusbphy_setuphandler_eventmanager_reset1 = cdcusbphy_setuphandler_reset_pending; +always @(*) begin + cdcusbphy_setuphandler_reset_clear <= 1'd0; + if ((cdcusbphy_setuphandler_eventmanager_pending_re & cdcusbphy_setuphandler_eventmanager_pending_r[1])) begin + cdcusbphy_setuphandler_reset_clear <= 1'd1; + end +end +assign cdcusbphy_setuphandler_irq = ((cdcusbphy_setuphandler_eventmanager_pending_status[0] & cdcusbphy_setuphandler_eventmanager_enable_storage[0]) | (cdcusbphy_setuphandler_eventmanager_pending_status[1] & cdcusbphy_setuphandler_eventmanager_enable_storage[1])); +assign cdcusbphy_setuphandler_packet_status = 1'd0; +assign cdcusbphy_setuphandler_reset_status = cdcusbphy_setuphandler_reset_trigger; +assign cdcusbphy_setuphandler_setuphandlerinner_empty = (~cdcusbphy_setuphandler_setuphandlerinner_readable); +assign cdcusbphy_setuphandler_csrfield_have = cdcusbphy_setuphandler_setuphandlerinner_readable; +assign cdcusbphy_setuphandler_csrfield_is_in = cdcusbphy_setuphandler_setuphandlerinner_is_in; +assign cdcusbphy_setuphandler_csrfield_epno = cdcusbphy_setuphandler_epno; +assign cdcusbphy_setuphandler_csrfield_pend = cdcusbphy_setuphandler_packet_pending; +assign cdcusbphy_setuphandler_csrfield_data1 = cdcusbphy_setuphandler_setuphandlerinner_have_data_stage; +assign cdcusbphy_setuphandler_csrfield_data0 = cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout; +assign cdcusbphy_setuphandler_setuphandlerinner_re = cdcusbphy_setuphandler_data_we; +always @(*) begin + cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din <= 8'd0; + cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we <= 1'd0; + if ((cdcusbphy_usb_core_tok == 4'd13)) begin + cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din <= cdcusbphy_setuphandler_data_recv_payload; + cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we <= cdcusbphy_setuphandler_data_recv_put; + end +end +assign cdcusbphy_setuphandler_packet_trigger = (cdcusbphy_setuphandler_setuphandlerinner_readable & cdcusbphy_usb_core_setup); +assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable & ((~cdcusbphy_setuphandler_setuphandlerinner_readable) | cdcusbphy_setuphandler_setuphandlerinner_re)); +assign cdcusbphy_setuphandler_setuphandlerinner_level1 = (cdcusbphy_setuphandler_setuphandlerinner_level0 + cdcusbphy_setuphandler_setuphandlerinner_readable); +always @(*) begin + cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= 4'd0; + if (cdcusbphy_setuphandler_setuphandlerinner_replace) begin + cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= (cdcusbphy_setuphandler_setuphandlerinner_produce - 1'd1); + end else begin + cdcusbphy_setuphandler_setuphandlerinner_wrport_adr <= cdcusbphy_setuphandler_setuphandlerinner_produce; + end +end +assign cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w = cdcusbphy_setuphandler_setuphandlerinner_syncfifo_din; +assign cdcusbphy_setuphandler_setuphandlerinner_wrport_we = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable | cdcusbphy_setuphandler_setuphandlerinner_replace)); +assign cdcusbphy_setuphandler_setuphandlerinner_do_read = (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re); +assign cdcusbphy_setuphandler_setuphandlerinner_rdport_adr = cdcusbphy_setuphandler_setuphandlerinner_consume; +assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_dout = cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r; +assign cdcusbphy_setuphandler_setuphandlerinner_rdport_re = cdcusbphy_setuphandler_setuphandlerinner_do_read; +assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable = (cdcusbphy_setuphandler_setuphandlerinner_level0 != 4'd10); +assign cdcusbphy_setuphandler_setuphandlerinner_syncfifo_readable = (cdcusbphy_setuphandler_setuphandlerinner_level0 != 1'd0); +assign cdcusbphy_inhandler_ep_stall_mask = (1'd1 <<< cdcusbphy_inhandler_csrfield_epno); +assign cdcusbphy_inhandler_stalled = (cdcusbphy_inhandler_stall_status >>> cdcusbphy_usb_core_endp); +assign cdcusbphy_inhandler_data_buf_reset = (cdcusbphy_inhandler_csrfield_reset | ((cdcusbphy_usb_core_commit & cdcusbphy_inhandler_transmitted) & cdcusbphy_inhandler_queued)); +assign cdcusbphy_inhandler_response = ((cdcusbphy_inhandler_queued & cdcusbphy_inhandler_is_our_packet) & cdcusbphy_inhandler_is_in_packet); +assign cdcusbphy_inhandler_csrfield_have = cdcusbphy_inhandler_syncfifobuffered_readable; +assign cdcusbphy_inhandler_csrfield_idle = (~cdcusbphy_inhandler_queued); +assign cdcusbphy_inhandler_csrfield_pend = cdcusbphy_inhandler_packet_pending; +assign cdcusbphy_inhandler_packet_trigger = ((~cdcusbphy_inhandler_queued) & cdcusbphy_inhandler_was_queued); +assign cdcusbphy_inhandler_dtb = (cdcusbphy_inhandler_dtbs >>> cdcusbphy_usb_core_endp); +assign cdcusbphy_inhandler_data_out = cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout; +assign cdcusbphy_inhandler_data_out_have = cdcusbphy_inhandler_syncfifobuffered_readable; +assign cdcusbphy_inhandler_syncfifobuffered_re = ((cdcusbphy_inhandler_data_out_advance & cdcusbphy_inhandler_is_in_packet) & cdcusbphy_inhandler_is_our_packet); +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_we = cdcusbphy_inhandler_data_re; +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_din = cdcusbphy_inhandler_data_storage; +assign cdcusbphy_inhandler_is_our_packet = (cdcusbphy_inhandler_csrfield_epno == cdcusbphy_usb_core_endp); +assign cdcusbphy_inhandler_is_in_packet = (cdcusbphy_usb_core_tok == 4'd9); +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_re = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable & ((~cdcusbphy_inhandler_syncfifobuffered_readable) | cdcusbphy_inhandler_syncfifobuffered_re)); +assign cdcusbphy_inhandler_syncfifobuffered_level1 = (cdcusbphy_inhandler_syncfifobuffered_level0 + cdcusbphy_inhandler_syncfifobuffered_readable); +always @(*) begin + cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= 6'd0; + if (cdcusbphy_inhandler_syncfifobuffered_replace) begin + cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= (cdcusbphy_inhandler_syncfifobuffered_produce - 1'd1); + end else begin + cdcusbphy_inhandler_syncfifobuffered_wrport_adr <= cdcusbphy_inhandler_syncfifobuffered_produce; + end +end +assign cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w = cdcusbphy_inhandler_syncfifobuffered_syncfifo_din; +assign cdcusbphy_inhandler_syncfifobuffered_wrport_we = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & (cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable | cdcusbphy_inhandler_syncfifobuffered_replace)); +assign cdcusbphy_inhandler_syncfifobuffered_do_read = (cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable & cdcusbphy_inhandler_syncfifobuffered_syncfifo_re); +assign cdcusbphy_inhandler_syncfifobuffered_rdport_adr = cdcusbphy_inhandler_syncfifobuffered_consume; +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_dout = cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r; +assign cdcusbphy_inhandler_syncfifobuffered_rdport_re = cdcusbphy_inhandler_syncfifobuffered_do_read; +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable = (cdcusbphy_inhandler_syncfifobuffered_level0 != 7'd64); +assign cdcusbphy_inhandler_syncfifobuffered_syncfifo_readable = (cdcusbphy_inhandler_syncfifobuffered_level0 != 1'd0); +assign cdcusbphy_inhandler_done0 = cdcusbphy_inhandler_packet_status; +assign cdcusbphy_inhandler_done1 = cdcusbphy_inhandler_packet_pending; +always @(*) begin + cdcusbphy_inhandler_packet_clear <= 1'd0; + if ((cdcusbphy_inhandler_pending_re & cdcusbphy_inhandler_pending_r)) begin + cdcusbphy_inhandler_packet_clear <= 1'd1; + end +end +assign cdcusbphy_inhandler_irq = (cdcusbphy_inhandler_pending_status & cdcusbphy_inhandler_enable_storage); +assign cdcusbphy_inhandler_packet_status = 1'd0; +always @(*) begin + cdcusbphy_outhandler_ep_mask <= 16'd1; + if ((cdcusbphy_usb_core_setup | cdcusbphy_usb_core_commit)) begin + cdcusbphy_outhandler_ep_mask <= (1'd1 <<< cdcusbphy_usb_core_endp); + end else begin + cdcusbphy_outhandler_ep_mask <= (1'd1 <<< cdcusbphy_outhandler_csrfield_epno0); + end +end +assign cdcusbphy_outhandler_stalled = (cdcusbphy_outhandler_stall_status >>> cdcusbphy_usb_core_endp); +assign cdcusbphy_outhandler_enabled = (cdcusbphy_outhandler_enable_status >>> cdcusbphy_usb_core_endp); +assign cdcusbphy_outhandler_is_out_packet = (cdcusbphy_usb_core_tok == 1'd1); +assign cdcusbphy_outhandler_response = ((cdcusbphy_outhandler_enabled & cdcusbphy_outhandler_is_out_packet) & (~cdcusbphy_outhandler_packet_pending)); +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_din = cdcusbphy_outhandler_data_recv_payload; +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_we = (cdcusbphy_outhandler_data_recv_put & cdcusbphy_outhandler_responding); +assign cdcusbphy_outhandler_data_buf_reset = cdcusbphy_outhandler_csrfield_reset; +assign cdcusbphy_outhandler_csrfield_data = cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout; +assign cdcusbphy_outhandler_syncfifobuffered_re = cdcusbphy_outhandler_data_we; +assign cdcusbphy_outhandler_csrfield_epno1 = cdcusbphy_outhandler_epno; +assign cdcusbphy_outhandler_csrfield_have = cdcusbphy_outhandler_syncfifobuffered_readable; +assign cdcusbphy_outhandler_csrfield_pend = cdcusbphy_outhandler_packet_pending; +assign cdcusbphy_outhandler_packet_trigger = (cdcusbphy_outhandler_responding & cdcusbphy_usb_core_commit); +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_re = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable & ((~cdcusbphy_outhandler_syncfifobuffered_readable) | cdcusbphy_outhandler_syncfifobuffered_re)); +assign cdcusbphy_outhandler_syncfifobuffered_level1 = (cdcusbphy_outhandler_syncfifobuffered_level0 + cdcusbphy_outhandler_syncfifobuffered_readable); +always @(*) begin + cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= 7'd0; + if (cdcusbphy_outhandler_syncfifobuffered_replace) begin + cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= (cdcusbphy_outhandler_syncfifobuffered_produce - 1'd1); + end else begin + cdcusbphy_outhandler_syncfifobuffered_wrport_adr <= cdcusbphy_outhandler_syncfifobuffered_produce; + end +end +assign cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w = cdcusbphy_outhandler_syncfifobuffered_syncfifo_din; +assign cdcusbphy_outhandler_syncfifobuffered_wrport_we = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & (cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable | cdcusbphy_outhandler_syncfifobuffered_replace)); +assign cdcusbphy_outhandler_syncfifobuffered_do_read = (cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable & cdcusbphy_outhandler_syncfifobuffered_syncfifo_re); +assign cdcusbphy_outhandler_syncfifobuffered_rdport_adr = cdcusbphy_outhandler_syncfifobuffered_consume; +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_dout = cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r; +assign cdcusbphy_outhandler_syncfifobuffered_rdport_re = cdcusbphy_outhandler_syncfifobuffered_do_read; +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable = (cdcusbphy_outhandler_syncfifobuffered_level0 != 7'd66); +assign cdcusbphy_outhandler_syncfifobuffered_syncfifo_readable = (cdcusbphy_outhandler_syncfifobuffered_level0 != 1'd0); +assign cdcusbphy_outhandler_done0 = cdcusbphy_outhandler_packet_status; +assign cdcusbphy_outhandler_done1 = cdcusbphy_outhandler_packet_pending; +always @(*) begin + cdcusbphy_outhandler_packet_clear <= 1'd0; + if ((cdcusbphy_outhandler_pending_re & cdcusbphy_outhandler_pending_r)) begin + cdcusbphy_outhandler_packet_clear <= 1'd1; + end +end +assign cdcusbphy_outhandler_irq = (cdcusbphy_outhandler_pending_status & cdcusbphy_outhandler_enable_storage); +assign cdcusbphy_outhandler_packet_status = 1'd0; +assign cdcusbphy_ev_irq = ((cdcusbphy_setuphandler_irq | cdcusbphy_inhandler_irq) | cdcusbphy_outhandler_irq); +always @(*) begin + cdcusbphy_setuphandler_data_recv_put <= 1'd0; + cdcusbphy_inhandler_dtb_reset <= 1'd0; + cdcusbphy_usb_core_data_send_have <= 1'd0; + subfragments_clockdomainsrenamer_next_state1 <= 3'd0; + cdcusbphy_usb_core_data_send_payload <= 8'd0; + cdcusbphy_usb_core_addr_csrtransform_next_value <= 7'd0; + cdcusbphy_inhandler_data_out_advance <= 1'd0; + cdcusbphy_usb_core_addr_csrtransform_next_value_ce <= 1'd0; + cdcusbphy_outhandler_data_recv_put <= 1'd0; + cdcusbphy_usb_core_arm <= 1'd0; + cdcusbphy_outhandler_data_recv_payload <= 8'd0; + cdcusbphy_usb_core_sta <= 1'd0; + cdcusbphy_setuphandler_begin <= 1'd0; + cdcusbphy_setuphandler_data_recv_payload <= 8'd0; + subfragments_clockdomainsrenamer_next_state1 <= subfragments_clockdomainsrenamer_state1; + case (subfragments_clockdomainsrenamer_state1) + 1'd1: begin + if (cdcusbphy_usb_core_idle) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end else begin + if ((cdcusbphy_usb_core_tok == 4'd13)) begin + subfragments_clockdomainsrenamer_next_state1 <= 2'd3; + cdcusbphy_setuphandler_begin <= 1'd1; + cdcusbphy_inhandler_dtb_reset <= 1'd1; + cdcusbphy_usb_core_sta <= 1'd0; + cdcusbphy_usb_core_arm <= 1'd1; + end else begin + if ((cdcusbphy_usb_core_tok == 4'd9)) begin + subfragments_clockdomainsrenamer_next_state1 <= 3'd4; + cdcusbphy_usb_core_sta <= cdcusbphy_inhandler_stalled; + cdcusbphy_usb_core_arm <= cdcusbphy_inhandler_response; + end else begin + if ((cdcusbphy_usb_core_tok == 1'd1)) begin + subfragments_clockdomainsrenamer_next_state1 <= 3'd5; + cdcusbphy_usb_core_sta <= cdcusbphy_outhandler_stalled; + cdcusbphy_usb_core_arm <= cdcusbphy_outhandler_response; + end else begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end + end + end + end + end + 2'd2: begin + cdcusbphy_usb_core_data_send_payload <= cdcusbphy_debug_bridge_sink_data; + cdcusbphy_usb_core_data_send_have <= cdcusbphy_debug_bridge_sink_valid; + cdcusbphy_usb_core_sta <= 1'd0; + if ((cdcusbphy_usb_core_endp == 1'd0)) begin + cdcusbphy_usb_core_arm <= (cdcusbphy_debug_bridge_send_ack | cdcusbphy_debug_bridge_sink_valid); + end else begin + cdcusbphy_usb_core_arm <= 1'd0; + end + if ((~cdcusbphy_debug_packet_detected)) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end + end + 2'd3: begin + cdcusbphy_setuphandler_data_recv_payload <= cdcusbphy_usb_core_data_recv_payload; + cdcusbphy_setuphandler_data_recv_put <= cdcusbphy_usb_core_data_recv_put; + cdcusbphy_usb_core_sta <= 1'd0; + cdcusbphy_usb_core_arm <= 1'd1; + if (cdcusbphy_debug_packet_detected) begin + subfragments_clockdomainsrenamer_next_state1 <= 2'd2; + end + if (cdcusbphy_usb_core_end) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end + end + 3'd4: begin + if ((cdcusbphy_usb_core_tok == 4'd9)) begin + cdcusbphy_usb_core_data_send_have <= cdcusbphy_inhandler_data_out_have; + cdcusbphy_usb_core_data_send_payload <= cdcusbphy_inhandler_data_out; + cdcusbphy_inhandler_data_out_advance <= cdcusbphy_usb_core_data_send_get; + cdcusbphy_usb_core_sta <= cdcusbphy_inhandler_stalled; + cdcusbphy_usb_core_arm <= cdcusbphy_inhandler_response; + if (cdcusbphy_usb_core_end) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end + end + end + 3'd5: begin + if ((cdcusbphy_usb_core_tok == 1'd1)) begin + cdcusbphy_outhandler_data_recv_payload <= cdcusbphy_usb_core_data_recv_payload; + cdcusbphy_outhandler_data_recv_put <= cdcusbphy_usb_core_data_recv_put; + cdcusbphy_usb_core_sta <= cdcusbphy_outhandler_stalled; + cdcusbphy_usb_core_arm <= cdcusbphy_outhandler_response; + if (cdcusbphy_usb_core_end) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd0; + end + end + end + default: begin + cdcusbphy_usb_core_addr_csrtransform_next_value <= cdcusbphy_csrstorage_storage; + cdcusbphy_usb_core_addr_csrtransform_next_value_ce <= 1'd1; + if (cdcusbphy_usb_core_start) begin + subfragments_clockdomainsrenamer_next_state1 <= 1'd1; + end + end + endcase +end +always @(*) begin + cdcusbphy_sink_payload_data <= 8'd0; + cdcusbphy_source_ready <= 1'd0; + cdcusbphy_new_address_fsm_t_next_value4 <= 7'd0; + cdcusbphy_new_address_fsm_t_next_value_ce4 <= 1'd0; + cdcusbphy_rts_fsm_t_next_value5 <= 1'd0; + cdcusbphy_rts_fsm_t_next_value_ce5 <= 1'd0; + cdcusbphy_dtr_fsm_t_next_value6 <= 1'd0; + cdcusbphy_dtr_fsm_t_next_value_ce6 <= 1'd0; + cdcusbphy_bytes_remaining_fsm_f_next_value0 <= 6'd0; + cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd0; + cdcusbphy_bytes_addr_fsm_f_next_value1 <= 9'd0; + cdcusbphy_setuphandler_data_we <= 1'd0; + cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd0; + subfragments_next_state <= 3'd0; + cdcusbphy_setup_index_fsm_next_value0 <= 4'd0; + cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd0; + cdcusbphy_outhandler_pending_re <= 1'd0; + cdcusbphy_outhandler_pending_r <= 1'd0; + cdcusbphy_csrtransform_address_re <= 1'd0; + cdcusbphy_inhandler_pending_r <= 1'd0; + cdcusbphy_csrtransform_address_addr0 <= 7'd0; + cdcusbphy_inhandler_pending_re <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd0; + cdcusbphy_csrtransform_in_data_re <= 1'd0; + cdcusbphy_csrtransform_in_data_data0 <= 8'd0; + cdcusbphy_data_d1_fsm_t_next_value0 <= 8'd0; + cdcusbphy_csrtransform_in_ctrl_re <= 1'd0; + cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd0; + cdcusbphy_csrtransform_in_ctrl_epno0 <= 4'd0; + cdcusbphy_data_d2_fsm_t_next_value1 <= 8'd0; + cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd0; + cdcusbphy_re_d1_fsm_t_next_value2 <= 1'd0; + cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd0; + cdcusbphy_re_d2_fsm_t_next_value3 <= 1'd0; + cdcusbphy_csrtransform_out_ctrl_re <= 1'd0; + cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd0; + cdcusbphy_csrtransform_out_ctrl_epno0 <= 4'd0; + cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd0; + cdcusbphy_usbPacket_fsm_cases_next_value0 <= 32'd0; + cdcusbphy_outhandler_data_we <= 1'd0; + cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd0; + cdcusbphy_sink_valid <= 1'd0; + cdcusbphy_wLength_fsm_cases_next_value1 <= 8'd0; + cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd0; + subfragments_next_state <= subfragments_state; + case (subfragments_state) + 1'd1: begin + cdcusbphy_csrtransform_out_ctrl_epno0 <= 1'd0; + cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd1; + cdcusbphy_csrtransform_out_ctrl_re <= 1'd1; + if (cdcusbphy_setuphandler_csrfield_have) begin + subfragments_next_state <= 3'd4; + cdcusbphy_setup_index_fsm_next_value0 <= 1'd0; + cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd1; + cdcusbphy_outhandler_pending_r <= 1'd1; + cdcusbphy_outhandler_pending_re <= 1'd1; + end else begin + if (cdcusbphy_outhandler_csrfield_have) begin + end + end + if (cdcusbphy_outhandler_pending_status) begin + cdcusbphy_outhandler_pending_r <= 1'd1; + cdcusbphy_outhandler_pending_re <= 1'd1; + if (((cdcusbphy_outhandler_csrfield_epno1 == 2'd2) & cdcusbphy_outhandler_csrfield_pend)) begin + subfragments_next_state <= 2'd3; + end + end + if ((cdcusbphy_source_valid & cdcusbphy_configured)) begin + subfragments_next_state <= 2'd2; + end + end + 2'd2: begin + cdcusbphy_csrtransform_in_data_data0 <= cdcusbphy_source_payload_data; + cdcusbphy_csrtransform_in_data_re <= (cdcusbphy_delayed_re & cdcusbphy_source_valid); + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + cdcusbphy_source_ready <= (cdcusbphy_delayed_re & cdcusbphy_source_valid); + if (cdcusbphy_source_valid) begin + cdcusbphy_delayed_re_fsm_next_value1 <= cdcusbphy_source_valid; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + end else begin + cdcusbphy_csrtransform_in_ctrl_epno0 <= 2'd2; + cdcusbphy_csrtransform_in_ctrl_re <= 1'd1; + subfragments_next_state <= 3'd6; + end + end + 2'd3: begin + cdcusbphy_sink_payload_data <= cdcusbphy_data_d2; + cdcusbphy_outhandler_data_we <= ((cdcusbphy_delayed_re & cdcusbphy_outhandler_csrfield_have) & cdcusbphy_sink_ready); + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + cdcusbphy_sink_valid <= ((cdcusbphy_re_d2 & cdcusbphy_outhandler_csrfield_have) & cdcusbphy_sink_ready); + if (cdcusbphy_outhandler_csrfield_have) begin + cdcusbphy_delayed_re_fsm_next_value1 <= cdcusbphy_outhandler_csrfield_have; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + if (cdcusbphy_sink_ready) begin + cdcusbphy_data_d1_fsm_t_next_value0 <= cdcusbphy_outhandler_csrfield_data; + cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd1; + cdcusbphy_data_d2_fsm_t_next_value1 <= cdcusbphy_data_d1; + cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd1; + cdcusbphy_re_d1_fsm_t_next_value2 <= cdcusbphy_delayed_re; + cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd1; + cdcusbphy_re_d2_fsm_t_next_value3 <= cdcusbphy_re_d1; + cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd1; + end + end else begin + cdcusbphy_data_d1_fsm_t_next_value0 <= 1'd0; + cdcusbphy_data_d1_fsm_t_next_value_ce0 <= 1'd1; + cdcusbphy_data_d2_fsm_t_next_value1 <= 1'd0; + cdcusbphy_data_d2_fsm_t_next_value_ce1 <= 1'd1; + cdcusbphy_re_d1_fsm_t_next_value2 <= 1'd0; + cdcusbphy_re_d1_fsm_t_next_value_ce2 <= 1'd1; + cdcusbphy_re_d2_fsm_t_next_value3 <= 1'd0; + cdcusbphy_re_d2_fsm_t_next_value_ce3 <= 1'd1; + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + subfragments_next_state <= 1'd0; + end + end + 3'd4: begin + if (cdcusbphy_setuphandler_csrfield_have) begin + cdcusbphy_setup_index_fsm_next_value0 <= (cdcusbphy_setup_index + 1'd1); + cdcusbphy_setup_index_fsm_next_value_ce0 <= 1'd1; + case (cdcusbphy_setup_index) + 1'd0: begin + cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0}; + cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1; + end + 1'd1: begin + cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0}; + cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1; + end + 2'd2: begin + cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0}; + cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1; + end + 2'd3: begin + cdcusbphy_usbPacket_fsm_cases_next_value0 <= {cdcusbphy_usbPacket[23:0], cdcusbphy_setuphandler_csrfield_data0}; + cdcusbphy_usbPacket_fsm_cases_next_value_ce0 <= 1'd1; + end + 3'd6: begin + cdcusbphy_wLength_fsm_cases_next_value1 <= cdcusbphy_setuphandler_csrfield_data0; + cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd1; + end + 3'd7: begin + if ((cdcusbphy_setuphandler_csrfield_data0 > 1'd0)) begin + cdcusbphy_wLength_fsm_cases_next_value1 <= 8'd255; + cdcusbphy_wLength_fsm_cases_next_value_ce1 <= 1'd1; + end + end + endcase + cdcusbphy_setuphandler_data_we <= 1'd1; + end + if ((cdcusbphy_setup_index == 4'd10)) begin + cdcusbphy_csrtransform_in_ctrl_epno0 <= 1'd0; + cdcusbphy_csrtransform_in_ctrl_re <= 1'd1; + subfragments_next_state <= 3'd6; + if ((cdcusbphy_wRequestAndType == 3'd5)) begin + cdcusbphy_new_address_fsm_t_next_value4 <= cdcusbphy_wValue[14:8]; + cdcusbphy_new_address_fsm_t_next_value_ce4 <= 1'd1; + subfragments_next_state <= 3'd6; + end else begin + if ((cdcusbphy_wRequestAndType == 14'd8482)) begin + cdcusbphy_rts_fsm_t_next_value5 <= cdcusbphy_wValue[9]; + cdcusbphy_rts_fsm_t_next_value_ce5 <= 1'd1; + cdcusbphy_dtr_fsm_t_next_value6 <= cdcusbphy_wValue[8]; + cdcusbphy_dtr_fsm_t_next_value_ce6 <= 1'd1; + subfragments_next_state <= 3'd6; + end else begin + if ((cdcusbphy_setuphandler_csrfield_is_in & (cdcusbphy_response_len > 1'd0))) begin + subfragments_next_state <= 3'd5; + if ((cdcusbphy_response_len > cdcusbphy_wLength)) begin + cdcusbphy_bytes_remaining_fsm_f_next_value0 <= cdcusbphy_wLength; + cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1; + end else begin + cdcusbphy_bytes_remaining_fsm_f_next_value0 <= cdcusbphy_response_len; + cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1; + end + cdcusbphy_bytes_addr_fsm_f_next_value1 <= cdcusbphy_response_addr; + cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd1; + end + end + end + end + end + 3'd5: begin + cdcusbphy_csrtransform_in_data_data0 <= cdcusbphy_dat_r; + cdcusbphy_csrtransform_in_data_re <= cdcusbphy_delayed_re; + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd0; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + if (cdcusbphy_bytes_remaining) begin + cdcusbphy_delayed_re_fsm_next_value1 <= 1'd1; + cdcusbphy_delayed_re_fsm_next_value_ce1 <= 1'd1; + cdcusbphy_bytes_addr_fsm_f_next_value1 <= (cdcusbphy_bytes_addr + 1'd1); + cdcusbphy_bytes_addr_fsm_f_next_value_ce1 <= 1'd1; + cdcusbphy_bytes_remaining_fsm_f_next_value0 <= (cdcusbphy_bytes_remaining - 1'd1); + cdcusbphy_bytes_remaining_fsm_f_next_value_ce0 <= 1'd1; + end else begin + if (cdcusbphy_inhandler_pending_status) begin + subfragments_next_state <= 3'd6; + end + end + end + 3'd6: begin + cdcusbphy_outhandler_data_we <= 1'd1; + if (cdcusbphy_inhandler_pending_status) begin + cdcusbphy_inhandler_pending_r <= 1'd1; + cdcusbphy_inhandler_pending_re <= 1'd1; + subfragments_next_state <= 1'd0; + end + end + 3'd7: begin + if ((cdcusbphy_inhandler_pending_status & cdcusbphy_outhandler_pending_status)) begin + cdcusbphy_inhandler_pending_r <= 1'd1; + cdcusbphy_inhandler_pending_re <= 1'd1; + cdcusbphy_outhandler_pending_r <= 1'd1; + cdcusbphy_outhandler_pending_re <= 1'd1; + subfragments_next_state <= 1'd0; + end + end + default: begin + cdcusbphy_csrtransform_address_addr0 <= cdcusbphy_new_address; + cdcusbphy_csrtransform_address_re <= 1'd1; + cdcusbphy_csrtransform_out_ctrl_epno0 <= 2'd2; + cdcusbphy_csrtransform_out_ctrl_enable0 <= 1'd1; + cdcusbphy_csrtransform_out_ctrl_re <= 1'd1; + subfragments_next_state <= 1'd1; + end + endcase +end +assign tx0 = tx_status; +assign tx1 = tx_pending; +always @(*) begin + tx_clear <= 1'd0; + if ((pending_re & pending_r[0])) begin + tx_clear <= 1'd1; + end +end +assign rx0 = rx_status; +assign rx1 = rx_pending; +always @(*) begin + rx_clear <= 1'd0; + if ((pending_re & pending_r[1])) begin + rx_clear <= 1'd1; + end +end +assign irq = ((pending_status[0] & enable_storage[0]) | (pending_status[1] & enable_storage[1])); +assign tx_status = tx_trigger; +assign rx_status = rx_trigger; +assign o = (toggle_o ^ toggle_o_r); +assign asyncfifo0_asyncfifo0_din = {asyncfifo0_fifo_in_last, asyncfifo0_fifo_in_first, asyncfifo0_fifo_in_payload_data}; +assign {asyncfifo0_fifo_out_last, asyncfifo0_fifo_out_first, asyncfifo0_fifo_out_payload_data} = asyncfifo0_asyncfifo0_dout; +assign asyncfifo0_sink_ready = asyncfifo0_asyncfifo0_writable; +assign asyncfifo0_asyncfifo0_we = asyncfifo0_sink_valid; +assign asyncfifo0_fifo_in_first = asyncfifo0_sink_first; +assign asyncfifo0_fifo_in_last = asyncfifo0_sink_last; +assign asyncfifo0_fifo_in_payload_data = asyncfifo0_sink_payload_data; +assign asyncfifo0_source_valid = asyncfifo0_asyncfifo0_readable; +assign asyncfifo0_source_first = asyncfifo0_fifo_out_first; +assign asyncfifo0_source_last = asyncfifo0_fifo_out_last; +assign asyncfifo0_source_payload_data = asyncfifo0_fifo_out_payload_data; +assign asyncfifo0_asyncfifo0_re = asyncfifo0_source_ready; +assign asyncfifo0_graycounter0_ce = (asyncfifo0_asyncfifo0_writable & asyncfifo0_asyncfifo0_we); +assign asyncfifo0_graycounter1_ce = (asyncfifo0_asyncfifo0_readable & asyncfifo0_asyncfifo0_re); +assign asyncfifo0_asyncfifo0_writable = (((asyncfifo0_graycounter0_q[2] == asyncfifo0_consume_wdomain[2]) | (asyncfifo0_graycounter0_q[1] == asyncfifo0_consume_wdomain[1])) | (asyncfifo0_graycounter0_q[0] != asyncfifo0_consume_wdomain[0])); +assign asyncfifo0_asyncfifo0_readable = (asyncfifo0_graycounter1_q != asyncfifo0_produce_rdomain); +assign asyncfifo0_wrport_adr = asyncfifo0_graycounter0_q_binary[1:0]; +assign asyncfifo0_wrport_dat_w = asyncfifo0_asyncfifo0_din; +assign asyncfifo0_wrport_we = asyncfifo0_graycounter0_ce; +assign asyncfifo0_rdport_adr = asyncfifo0_graycounter1_q_next_binary[1:0]; +assign asyncfifo0_asyncfifo0_dout = asyncfifo0_rdport_dat_r; +always @(*) begin + asyncfifo0_graycounter0_q_next_binary <= 3'd0; + if (asyncfifo0_graycounter0_ce) begin + asyncfifo0_graycounter0_q_next_binary <= (asyncfifo0_graycounter0_q_binary + 1'd1); + end else begin + asyncfifo0_graycounter0_q_next_binary <= asyncfifo0_graycounter0_q_binary; + end +end +assign asyncfifo0_graycounter0_q_next = (asyncfifo0_graycounter0_q_next_binary ^ asyncfifo0_graycounter0_q_next_binary[2:1]); +always @(*) begin + asyncfifo0_graycounter1_q_next_binary <= 3'd0; + if (asyncfifo0_graycounter1_ce) begin + asyncfifo0_graycounter1_q_next_binary <= (asyncfifo0_graycounter1_q_binary + 1'd1); + end else begin + asyncfifo0_graycounter1_q_next_binary <= asyncfifo0_graycounter1_q_binary; + end +end +assign asyncfifo0_graycounter1_q_next = (asyncfifo0_graycounter1_q_next_binary ^ asyncfifo0_graycounter1_q_next_binary[2:1]); +assign asyncfifo1_asyncfifo1_din = {asyncfifo1_fifo_in_last, asyncfifo1_fifo_in_first, asyncfifo1_fifo_in_payload_data}; +assign {asyncfifo1_fifo_out_last, asyncfifo1_fifo_out_first, asyncfifo1_fifo_out_payload_data} = asyncfifo1_asyncfifo1_dout; +assign asyncfifo1_sink_ready = asyncfifo1_asyncfifo1_writable; +assign asyncfifo1_asyncfifo1_we = asyncfifo1_sink_valid; +assign asyncfifo1_fifo_in_first = asyncfifo1_sink_first; +assign asyncfifo1_fifo_in_last = asyncfifo1_sink_last; +assign asyncfifo1_fifo_in_payload_data = asyncfifo1_sink_payload_data; +assign asyncfifo1_source_valid = asyncfifo1_asyncfifo1_readable; +assign asyncfifo1_source_first = asyncfifo1_fifo_out_first; +assign asyncfifo1_source_last = asyncfifo1_fifo_out_last; +assign asyncfifo1_source_payload_data = asyncfifo1_fifo_out_payload_data; +assign asyncfifo1_asyncfifo1_re = asyncfifo1_source_ready; +assign asyncfifo1_graycounter2_ce = (asyncfifo1_asyncfifo1_writable & asyncfifo1_asyncfifo1_we); +assign asyncfifo1_graycounter3_ce = (asyncfifo1_asyncfifo1_readable & asyncfifo1_asyncfifo1_re); +assign asyncfifo1_asyncfifo1_writable = (((asyncfifo1_graycounter2_q[2] == asyncfifo1_consume_wdomain[2]) | (asyncfifo1_graycounter2_q[1] == asyncfifo1_consume_wdomain[1])) | (asyncfifo1_graycounter2_q[0] != asyncfifo1_consume_wdomain[0])); +assign asyncfifo1_asyncfifo1_readable = (asyncfifo1_graycounter3_q != asyncfifo1_produce_rdomain); +assign asyncfifo1_wrport_adr = asyncfifo1_graycounter2_q_binary[1:0]; +assign asyncfifo1_wrport_dat_w = asyncfifo1_asyncfifo1_din; +assign asyncfifo1_wrport_we = asyncfifo1_graycounter2_ce; +assign asyncfifo1_rdport_adr = asyncfifo1_graycounter3_q_next_binary[1:0]; +assign asyncfifo1_asyncfifo1_dout = asyncfifo1_rdport_dat_r; +always @(*) begin + asyncfifo1_graycounter2_q_next_binary <= 3'd0; + if (asyncfifo1_graycounter2_ce) begin + asyncfifo1_graycounter2_q_next_binary <= (asyncfifo1_graycounter2_q_binary + 1'd1); + end else begin + asyncfifo1_graycounter2_q_next_binary <= asyncfifo1_graycounter2_q_binary; + end +end +assign asyncfifo1_graycounter2_q_next = (asyncfifo1_graycounter2_q_next_binary ^ asyncfifo1_graycounter2_q_next_binary[2:1]); +always @(*) begin + asyncfifo1_graycounter3_q_next_binary <= 3'd0; + if (asyncfifo1_graycounter3_ce) begin + asyncfifo1_graycounter3_q_next_binary <= (asyncfifo1_graycounter3_q_binary + 1'd1); + end else begin + asyncfifo1_graycounter3_q_next_binary <= asyncfifo1_graycounter3_q_binary; + end +end +assign asyncfifo1_graycounter3_q_next = (asyncfifo1_graycounter3_q_next_binary ^ asyncfifo1_graycounter3_q_next_binary[2:1]); +always @(*) begin + basesoc_basesoc_dat_w <= 32'd0; + basesoc_basesoc_wishbone_ack <= 1'd0; + basesoc_next_state <= 1'd0; + basesoc_basesoc_wishbone_dat_r <= 32'd0; + basesoc_basesoc_adr <= 14'd0; + basesoc_basesoc_we <= 1'd0; + basesoc_next_state <= basesoc_state; + case (basesoc_state) + 1'd1: begin + basesoc_basesoc_wishbone_ack <= 1'd1; + basesoc_basesoc_wishbone_dat_r <= basesoc_basesoc_dat_r; + basesoc_next_state <= 1'd0; + end + default: begin + basesoc_basesoc_dat_w <= basesoc_basesoc_wishbone_dat_w; + if ((basesoc_basesoc_wishbone_cyc & basesoc_basesoc_wishbone_stb)) begin + basesoc_basesoc_adr <= basesoc_basesoc_wishbone_adr; + basesoc_basesoc_we <= (basesoc_basesoc_wishbone_we & (basesoc_basesoc_wishbone_sel != 1'd0)); + basesoc_next_state <= 1'd1; + end + end + endcase +end +assign basesoc_basesoc_wishbone_adr = wb_ctrl_adr; +assign basesoc_basesoc_wishbone_dat_w = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = basesoc_basesoc_wishbone_dat_r; +assign basesoc_basesoc_wishbone_sel = wb_ctrl_sel; +assign basesoc_basesoc_wishbone_cyc = wb_ctrl_cyc; +assign basesoc_basesoc_wishbone_stb = wb_ctrl_stb; +assign wb_ctrl_ack = basesoc_basesoc_wishbone_ack; +assign basesoc_basesoc_wishbone_we = wb_ctrl_we; +assign basesoc_basesoc_wishbone_cti = wb_ctrl_cti; +assign basesoc_basesoc_wishbone_bte = wb_ctrl_bte; +assign wb_ctrl_err = basesoc_basesoc_wishbone_err; +assign basesoc_csrbank0_sel = (basesoc_interface0_bank_bus_adr[13:9] == 1'd1); +assign basesoc_csrbank0_reset0_r = basesoc_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csrbank0_reset0_re <= 1'd0; + basesoc_csrbank0_reset0_we <= 1'd0; + if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 1'd0))) begin + basesoc_csrbank0_reset0_re <= basesoc_interface0_bank_bus_we; + basesoc_csrbank0_reset0_we <= (~basesoc_interface0_bank_bus_we); + end +end +assign basesoc_csrbank0_scratch0_r = basesoc_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csrbank0_scratch0_we <= 1'd0; + basesoc_csrbank0_scratch0_re <= 1'd0; + if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csrbank0_scratch0_re <= basesoc_interface0_bank_bus_we; + basesoc_csrbank0_scratch0_we <= (~basesoc_interface0_bank_bus_we); + end +end +assign basesoc_csrbank0_bus_errors_r = basesoc_interface0_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csrbank0_bus_errors_we <= 1'd0; + basesoc_csrbank0_bus_errors_re <= 1'd0; + if ((basesoc_csrbank0_sel & (basesoc_interface0_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csrbank0_bus_errors_re <= basesoc_interface0_bank_bus_we; + basesoc_csrbank0_bus_errors_we <= (~basesoc_interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign basesoc_csrbank0_reset0_w = reset_storage[1:0]; +assign basesoc_csrbank0_scratch0_w = scratch_storage[31:0]; +assign basesoc_csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = basesoc_csrbank0_bus_errors_we; +assign basesoc_csrbank1_sel = (basesoc_interface1_bank_bus_adr[13:9] == 1'd0); +assign rxtx_r = basesoc_interface1_bank_bus_dat_w[7:0]; +always @(*) begin + rxtx_re <= 1'd0; + rxtx_we <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 1'd0))) begin + rxtx_re <= basesoc_interface1_bank_bus_we; + rxtx_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_txfull_r = basesoc_interface1_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csrbank1_txfull_we <= 1'd0; + basesoc_csrbank1_txfull_re <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 1'd1))) begin + basesoc_csrbank1_txfull_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_txfull_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_rxempty_r = basesoc_interface1_bank_bus_dat_w[0]; +always @(*) begin + basesoc_csrbank1_rxempty_we <= 1'd0; + basesoc_csrbank1_rxempty_re <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 2'd2))) begin + basesoc_csrbank1_rxempty_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_rxempty_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_ev_status_r = basesoc_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csrbank1_ev_status_re <= 1'd0; + basesoc_csrbank1_ev_status_we <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 2'd3))) begin + basesoc_csrbank1_ev_status_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_ev_status_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_ev_pending_r = basesoc_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csrbank1_ev_pending_re <= 1'd0; + basesoc_csrbank1_ev_pending_we <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd4))) begin + basesoc_csrbank1_ev_pending_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_ev_pending_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_ev_enable0_r = basesoc_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + basesoc_csrbank1_ev_enable0_we <= 1'd0; + basesoc_csrbank1_ev_enable0_re <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd5))) begin + basesoc_csrbank1_ev_enable0_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_ev_enable0_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_tuning_word0_r = basesoc_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + basesoc_csrbank1_tuning_word0_re <= 1'd0; + basesoc_csrbank1_tuning_word0_we <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd6))) begin + basesoc_csrbank1_tuning_word0_re <= basesoc_interface1_bank_bus_we; + basesoc_csrbank1_tuning_word0_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign configured_r = basesoc_interface1_bank_bus_dat_w[0]; +always @(*) begin + configured_re <= 1'd0; + configured_we <= 1'd0; + if ((basesoc_csrbank1_sel & (basesoc_interface1_bank_bus_adr[8:0] == 3'd7))) begin + configured_re <= basesoc_interface1_bank_bus_we; + configured_we <= (~basesoc_interface1_bank_bus_we); + end +end +assign basesoc_csrbank1_txfull_w = txfull_status; +assign txfull_we = basesoc_csrbank1_txfull_we; +assign basesoc_csrbank1_rxempty_w = rxempty_status; +assign rxempty_we = basesoc_csrbank1_rxempty_we; +always @(*) begin + status_status <= 2'd0; + status_status[0] <= tx0; + status_status[1] <= rx0; +end +assign basesoc_csrbank1_ev_status_w = status_status[1:0]; +assign status_we = basesoc_csrbank1_ev_status_we; +always @(*) begin + pending_status <= 2'd0; + pending_status[0] <= tx1; + pending_status[1] <= rx1; +end +assign basesoc_csrbank1_ev_pending_w = pending_status[1:0]; +assign pending_we = basesoc_csrbank1_ev_pending_we; +assign tx2 = enable_storage[0]; +assign rx2 = enable_storage[1]; +assign basesoc_csrbank1_ev_enable0_w = enable_storage[1:0]; +assign basesoc_csrbank1_tuning_word0_w = tuning_word_storage[31:0]; +assign basesoc_csr_interconnect_adr = basesoc_basesoc_adr; +assign basesoc_csr_interconnect_we = basesoc_basesoc_we; +assign basesoc_csr_interconnect_dat_w = basesoc_basesoc_dat_w; +assign basesoc_basesoc_dat_r = basesoc_csr_interconnect_dat_r; +assign basesoc_interface0_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_interface1_bank_bus_adr = basesoc_csr_interconnect_adr; +assign basesoc_interface0_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_interface1_bank_bus_we = basesoc_csr_interconnect_we; +assign basesoc_interface0_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_interface1_bank_bus_dat_w = basesoc_csr_interconnect_dat_w; +assign basesoc_csr_interconnect_dat_r = (basesoc_interface0_bank_bus_dat_r | basesoc_interface1_bank_bus_dat_r); +assign slice_proxy = 9'd1; +assign sdrio_clk = usb_48_clk; +assign sdrio_clk_1 = usb_48_clk; +assign cdcusbphy_usb_core_tx_nrzi_dat = multiregimpl0_regs2; +assign cdcusbphy_usb_core_tx_nrzi_oe1 = multiregimpl1_regs2; +assign cdcusbphy_usb_core_txstate_o_oe12 = multiregimpl2_regs; +assign cdcusbphy_usb_core_rx_payloadFifo_produce_rdomain = multiregimpl3_regs1; +assign cdcusbphy_usb_core_rx_payloadFifo_consume_wdomain = multiregimpl4_regs1; +assign cdcusbphy_usb_core_rx_flagsFifo_produce_rdomain = multiregimpl5_regs1; +assign cdcusbphy_usb_core_rx_flagsFifo_consume_wdomain = multiregimpl6_regs1; +assign rts = multiregimpl7_regs1; +assign dtr = multiregimpl8_regs1; +assign toggle_o = multiregimpl9_regs1; +assign asyncfifo0_produce_rdomain = multiregimpl10_regs1; +assign asyncfifo0_consume_wdomain = multiregimpl11_regs1; +assign asyncfifo1_produce_rdomain = multiregimpl12_regs1; +assign asyncfifo1_consume_wdomain = multiregimpl13_regs1; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge sdrio_clk) begin + inferedsdrtristate0_oe <= usb_iobuf_usb_tx_en; + inferedsdrtristate1_oe <= usb_iobuf_usb_tx_en; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + if (tx_clear) begin + tx_pending <= 1'd0; + end + tx_trigger_d <= tx_trigger; + if (((~tx_trigger) & tx_trigger_d)) begin + tx_pending <= 1'd1; + end + if (rx_clear) begin + rx_pending <= 1'd0; + end + rx_trigger_d <= rx_trigger; + if (((~rx_trigger) & rx_trigger_d)) begin + rx_pending <= 1'd1; + end + if (i) begin + toggle_i <= (~toggle_i); + end + asyncfifo0_graycounter0_q_binary <= asyncfifo0_graycounter0_q_next_binary; + asyncfifo0_graycounter0_q <= asyncfifo0_graycounter0_q_next; + asyncfifo1_graycounter3_q_binary <= asyncfifo1_graycounter3_q_next_binary; + asyncfifo1_graycounter3_q <= asyncfifo1_graycounter3_q_next; + basesoc_state <= basesoc_next_state; + basesoc_interface0_bank_bus_dat_r <= 1'd0; + if (basesoc_csrbank0_sel) begin + case (basesoc_interface0_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_reset0_w; + end + 1'd1: begin + basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_scratch0_w; + end + 2'd2: begin + basesoc_interface0_bank_bus_dat_r <= basesoc_csrbank0_bus_errors_w; + end + endcase + end + if (basesoc_csrbank0_reset0_re) begin + reset_storage[1:0] <= basesoc_csrbank0_reset0_r; + end + reset_re <= basesoc_csrbank0_reset0_re; + if (basesoc_csrbank0_scratch0_re) begin + scratch_storage[31:0] <= basesoc_csrbank0_scratch0_r; + end + scratch_re <= basesoc_csrbank0_scratch0_re; + bus_errors_re <= basesoc_csrbank0_bus_errors_re; + basesoc_interface1_bank_bus_dat_r <= 1'd0; + if (basesoc_csrbank1_sel) begin + case (basesoc_interface1_bank_bus_adr[8:0]) + 1'd0: begin + basesoc_interface1_bank_bus_dat_r <= rxtx_w; + end + 1'd1: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_txfull_w; + end + 2'd2: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_rxempty_w; + end + 2'd3: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_status_w; + end + 3'd4: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_pending_w; + end + 3'd5: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_ev_enable0_w; + end + 3'd6: begin + basesoc_interface1_bank_bus_dat_r <= basesoc_csrbank1_tuning_word0_w; + end + 3'd7: begin + basesoc_interface1_bank_bus_dat_r <= configured_w; + end + endcase + end + txfull_re <= basesoc_csrbank1_txfull_re; + rxempty_re <= basesoc_csrbank1_rxempty_re; + status_re <= basesoc_csrbank1_ev_status_re; + if (basesoc_csrbank1_ev_pending_re) begin + pending_r[1:0] <= basesoc_csrbank1_ev_pending_r; + end + pending_re <= basesoc_csrbank1_ev_pending_re; + if (basesoc_csrbank1_ev_enable0_re) begin + enable_storage[1:0] <= basesoc_csrbank1_ev_enable0_r; + end + enable_re <= basesoc_csrbank1_ev_enable0_re; + if (basesoc_csrbank1_tuning_word0_re) begin + tuning_word_storage[31:0] <= basesoc_csrbank1_tuning_word0_r; + end + tuning_word_re <= basesoc_csrbank1_tuning_word0_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + txfull_re <= 1'd0; + rxempty_re <= 1'd0; + tx_pending <= 1'd0; + tx_trigger_d <= 1'd0; + rx_pending <= 1'd0; + rx_trigger_d <= 1'd0; + status_re <= 1'd0; + pending_re <= 1'd0; + pending_r <= 2'd0; + enable_storage <= 2'd0; + enable_re <= 1'd0; + tuning_word_storage <= 32'd0; + tuning_word_re <= 1'd0; + asyncfifo0_graycounter0_q <= 3'd0; + asyncfifo0_graycounter0_q_binary <= 3'd0; + asyncfifo1_graycounter3_q <= 3'd0; + asyncfifo1_graycounter3_q_binary <= 3'd0; + basesoc_state <= 1'd0; + end + multiregimpl7_regs0 <= cdcusbphy_rts; + multiregimpl7_regs1 <= multiregimpl7_regs0; + multiregimpl8_regs0 <= cdcusbphy_dtr; + multiregimpl8_regs1 <= multiregimpl8_regs0; + multiregimpl11_regs0 <= asyncfifo0_graycounter1_q; + multiregimpl11_regs1 <= multiregimpl11_regs0; + multiregimpl12_regs0 <= asyncfifo1_graycounter2_q; + multiregimpl12_regs1 <= multiregimpl12_regs0; +end + +always @(posedge usb_12_clk) begin + cdcusbphy_usb_core_tx_bitstuff_valid_data <= (((~cdcusbphy_usb_core_tx_stall) & cdcusbphy_usb_core_tx_shifter_o_get) & cdcusbphy_usb_core_tx_i_oe); + subfragments_fsm_state <= subfragments_fsm_next_state; + if (cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value_ce0) begin + cdcusbphy_usb_core_tx_sync_pulse <= cdcusbphy_usb_core_tx_sync_pulse_csrtransform_txpipeline_next_value0; + end + if (cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value_ce1) begin + cdcusbphy_usb_core_tx_state_gray <= cdcusbphy_usb_core_tx_state_gray_csrtransform_txpipeline_next_value1; + end + if (cdcusbphy_usb_core_tx_shifter_ce) begin + cdcusbphy_usb_core_tx_shifter_pos <= (cdcusbphy_usb_core_tx_shifter_pos >>> 1'd1); + cdcusbphy_usb_core_tx_shifter_shifter <= (cdcusbphy_usb_core_tx_shifter_shifter >>> 1'd1); + if (cdcusbphy_usb_core_tx_shifter_empty) begin + cdcusbphy_usb_core_tx_shifter_shifter <= cdcusbphy_usb_core_tx_shifter_i_data; + cdcusbphy_usb_core_tx_shifter_pos <= 8'd128; + end + cdcusbphy_usb_core_tx_shifter_o_get <= cdcusbphy_usb_core_tx_shifter_empty; + end + if (cdcusbphy_usb_core_tx_shifter_reset) begin + cdcusbphy_usb_core_tx_shifter_o_get <= 1'd0; + cdcusbphy_usb_core_tx_shifter_shifter <= 8'd0; + cdcusbphy_usb_core_tx_shifter_pos <= 8'd1; + end + if (cdcusbphy_usb_core_tx_bitstuff_stuff_bit) begin + cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0; + end else begin + cdcusbphy_usb_core_tx_bitstuff_o_data <= cdcusbphy_usb_core_tx_bitstuff_i_data; + end + subfragments_resetinserter_state <= subfragments_resetinserter_next_state; + if (cdcusbphy_usb_core_tx_bitstuff_reset) begin + cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0; + subfragments_resetinserter_state <= 3'd0; + end + subfragments_txpacketsend_state <= subfragments_txpacketsend_next_state; + if (cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value_ce0) begin + cdcusbphy_usb_core_tx_i_oe <= cdcusbphy_usb_core_tx_i_oe_csrtransform_txpacketsend_next_value0; + end + if (cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value_ce1) begin + cdcusbphy_usb_core_txstate_pid <= cdcusbphy_usb_core_txstate_pid_csrtransform_txpacketsend_next_value1; + end + if (cdcusbphy_usb_core_txstate_i_data_strobe) begin + cdcusbphy_usb_core_txstate_crc_cur <= cdcusbphy_usb_core_txstate_crc_next; + end + if (cdcusbphy_usb_core_txstate_reset) begin + cdcusbphy_usb_core_txstate_crc_cur <= 16'd65535; + end + if (cdcusbphy_usb_core_rx_o_pkt_start) begin + cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd1; + end else begin + if (cdcusbphy_usb_core_rx_o_pkt_end) begin + cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd0; + end + end + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next_binary; + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_next; + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next_binary; + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_next; + subfragments_packetheaderdecode_state <= subfragments_packetheaderdecode_next_state; + if (cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value_ce0) begin + cdcusbphy_usb_core_o_pid <= cdcusbphy_usb_core_o_pid_csrtransform_packetheaderdecode_next_value0; + end + if (subfragments_packetheaderdecode_next_value_ce) begin + cdcusbphy_usb_core_o_addr[6:0] <= subfragments_packetheaderdecode_next_value; + end + if (cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value_ce1) begin + cdcusbphy_usb_core_endp4 <= cdcusbphy_usb_core_endp4_csrtransform_packetheaderdecode_next_value1; + end + if (cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value_ce2) begin + cdcusbphy_usb_core_o_endp <= cdcusbphy_usb_core_o_endp_csrtransform_packetheaderdecode_next_value2; + end + if (cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value_ce3) begin + cdcusbphy_usb_core_crc5 <= cdcusbphy_usb_core_crc5_csrtransform_packetheaderdecode_next_value3; + end + subfragments_clockdomainsrenamer_state0 <= subfragments_clockdomainsrenamer_next_state0; + if (cdcusbphy_usb_core_tok_csrtransform_f_next_value_ce0) begin + cdcusbphy_usb_core_tok <= cdcusbphy_usb_core_tok_csrtransform_f_next_value0; + end + if (cdcusbphy_usb_core_endp_csrtransform_f_next_value_ce1) begin + cdcusbphy_usb_core_endp <= cdcusbphy_usb_core_endp_csrtransform_f_next_value1; + end + if (cdcusbphy_usb_core_response_pid_csrtransform_t_next_value_ce) begin + cdcusbphy_usb_core_response_pid <= cdcusbphy_usb_core_response_pid_csrtransform_t_next_value; + end + if (cdcusbphy_usb_core_transfer_reset) begin + cdcusbphy_usb_core_tok <= 4'd0; + cdcusbphy_usb_core_endp <= 4'd0; + cdcusbphy_usb_core_response_pid <= 4'd0; + subfragments_clockdomainsrenamer_state0 <= 4'd1; + end + if (cdcusbphy_debug_bridge_byte_counter_reset) begin + cdcusbphy_debug_bridge_byte_counter <= 1'd0; + end else begin + if (cdcusbphy_debug_bridge_byte_counter_ce) begin + cdcusbphy_debug_bridge_byte_counter <= (cdcusbphy_debug_bridge_byte_counter + 1'd1); + end + end + if (cdcusbphy_debug_bridge_cmd_ce) begin + cdcusbphy_debug_bridge_cmd <= cdcusbphy_usb_core_data_recv_payload[7]; + end + if (cdcusbphy_debug_bridge_address_ce) begin + cdcusbphy_debug_bridge_address <= {cdcusbphy_usb_core_data_recv_payload, cdcusbphy_debug_bridge_address[31:8]}; + end + if (cdcusbphy_debug_bridge_rx_data_ce) begin + cdcusbphy_debug_bridge_data <= {cdcusbphy_usb_core_data_recv_payload, cdcusbphy_debug_bridge_data[31:8]}; + end + subfragments_usbwishbonebridge_state <= subfragments_usbwishbonebridge_next_state; + if (cdcusbphy_debug_bridge_reset) begin + subfragments_usbwishbonebridge_state <= 4'd0; + end + if (cdcusbphy_setuphandler_packet_clear) begin + cdcusbphy_setuphandler_packet_pending <= 1'd0; + end + if (cdcusbphy_setuphandler_packet_trigger) begin + cdcusbphy_setuphandler_packet_pending <= 1'd1; + end + if (cdcusbphy_setuphandler_reset_clear) begin + cdcusbphy_setuphandler_reset_pending <= 1'd0; + end + cdcusbphy_setuphandler_reset_trigger_d <= cdcusbphy_setuphandler_reset_trigger; + if (((~cdcusbphy_setuphandler_reset_trigger) & cdcusbphy_setuphandler_reset_trigger_d)) begin + cdcusbphy_setuphandler_reset_pending <= 1'd1; + end + if (cdcusbphy_setuphandler_data_recv_put) begin + if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 1'd0)) begin + cdcusbphy_setuphandler_epno <= cdcusbphy_usb_core_endp; + cdcusbphy_setuphandler_setuphandlerinner_is_in <= cdcusbphy_setuphandler_data_recv_payload[7]; + end else begin + if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 3'd6)) begin + if (cdcusbphy_setuphandler_data_recv_payload) begin + cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd1; + end + end else begin + if ((cdcusbphy_setuphandler_setuphandlerinner_data_byte == 3'd7)) begin + if (cdcusbphy_setuphandler_data_recv_payload) begin + cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd1; + end + end + end + end + cdcusbphy_setuphandler_setuphandlerinner_data_byte <= (cdcusbphy_setuphandler_setuphandlerinner_data_byte + 1'd1); + end + if (cdcusbphy_setuphandler_setuphandlerinner_syncfifo_re) begin + cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd1; + end else begin + if (cdcusbphy_setuphandler_setuphandlerinner_re) begin + cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0; + end + end + if (((cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable) & (~cdcusbphy_setuphandler_setuphandlerinner_replace))) begin + if ((cdcusbphy_setuphandler_setuphandlerinner_produce == 4'd9)) begin + cdcusbphy_setuphandler_setuphandlerinner_produce <= 1'd0; + end else begin + cdcusbphy_setuphandler_setuphandlerinner_produce <= (cdcusbphy_setuphandler_setuphandlerinner_produce + 1'd1); + end + end + if (cdcusbphy_setuphandler_setuphandlerinner_do_read) begin + if ((cdcusbphy_setuphandler_setuphandlerinner_consume == 4'd9)) begin + cdcusbphy_setuphandler_setuphandlerinner_consume <= 1'd0; + end else begin + cdcusbphy_setuphandler_setuphandlerinner_consume <= (cdcusbphy_setuphandler_setuphandlerinner_consume + 1'd1); + end + end + if (((cdcusbphy_setuphandler_setuphandlerinner_syncfifo_we & cdcusbphy_setuphandler_setuphandlerinner_syncfifo_writable) & (~cdcusbphy_setuphandler_setuphandlerinner_replace))) begin + if ((~cdcusbphy_setuphandler_setuphandlerinner_do_read)) begin + cdcusbphy_setuphandler_setuphandlerinner_level0 <= (cdcusbphy_setuphandler_setuphandlerinner_level0 + 1'd1); + end + end else begin + if (cdcusbphy_setuphandler_setuphandlerinner_do_read) begin + cdcusbphy_setuphandler_setuphandlerinner_level0 <= (cdcusbphy_setuphandler_setuphandlerinner_level0 - 1'd1); + end + end + if (cdcusbphy_setuphandler_inner_reset) begin + cdcusbphy_setuphandler_epno <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_level0 <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_produce <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_consume <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_data_byte <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_is_in <= 1'd0; + end + if (cdcusbphy_inhandler_csrfield_reset) begin + cdcusbphy_inhandler_stall_status <= 1'd0; + end else begin + if ((cdcusbphy_usb_core_setup | (cdcusbphy_inhandler_ctrl_re & (~cdcusbphy_inhandler_csrfield_stall)))) begin + cdcusbphy_inhandler_stall_status <= (cdcusbphy_inhandler_stall_status & (~cdcusbphy_inhandler_ep_stall_mask)); + end else begin + if (cdcusbphy_inhandler_ctrl_re) begin + cdcusbphy_inhandler_stall_status <= (cdcusbphy_inhandler_stall_status | cdcusbphy_inhandler_ep_stall_mask); + end + end + end + if (cdcusbphy_inhandler_csrfield_reset) begin + cdcusbphy_inhandler_queued <= 1'd0; + cdcusbphy_inhandler_was_queued <= 1'd0; + cdcusbphy_inhandler_transmitted <= 1'd0; + cdcusbphy_inhandler_dtbs <= 1'd1; + end else begin + if (cdcusbphy_inhandler_dtb_reset) begin + cdcusbphy_inhandler_dtbs <= (cdcusbphy_inhandler_dtbs | 1'd1); + end else begin + if ((cdcusbphy_inhandler_ctrl_re & (~cdcusbphy_inhandler_csrfield_stall))) begin + cdcusbphy_inhandler_queued <= 1'd1; + end else begin + if ((cdcusbphy_usb_core_poll & cdcusbphy_inhandler_response)) begin + cdcusbphy_inhandler_transmitted <= 1'd1; + end else begin + if ((((cdcusbphy_usb_core_commit & cdcusbphy_inhandler_transmitted) & cdcusbphy_inhandler_response) & (~cdcusbphy_inhandler_stalled))) begin + cdcusbphy_inhandler_queued <= 1'd0; + cdcusbphy_inhandler_transmitted <= 1'd0; + cdcusbphy_inhandler_dtbs <= (cdcusbphy_inhandler_dtbs ^ (1'd1 <<< cdcusbphy_inhandler_csrfield_epno)); + end else begin + cdcusbphy_inhandler_was_queued <= cdcusbphy_inhandler_queued; + end + end + end + end + end + if (cdcusbphy_inhandler_syncfifobuffered_syncfifo_re) begin + cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd1; + end else begin + if (cdcusbphy_inhandler_syncfifobuffered_re) begin + cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0; + end + end + if (((cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_inhandler_syncfifobuffered_replace))) begin + cdcusbphy_inhandler_syncfifobuffered_produce <= (cdcusbphy_inhandler_syncfifobuffered_produce + 1'd1); + end + if (cdcusbphy_inhandler_syncfifobuffered_do_read) begin + cdcusbphy_inhandler_syncfifobuffered_consume <= (cdcusbphy_inhandler_syncfifobuffered_consume + 1'd1); + end + if (((cdcusbphy_inhandler_syncfifobuffered_syncfifo_we & cdcusbphy_inhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_inhandler_syncfifobuffered_replace))) begin + if ((~cdcusbphy_inhandler_syncfifobuffered_do_read)) begin + cdcusbphy_inhandler_syncfifobuffered_level0 <= (cdcusbphy_inhandler_syncfifobuffered_level0 + 1'd1); + end + end else begin + if (cdcusbphy_inhandler_syncfifobuffered_do_read) begin + cdcusbphy_inhandler_syncfifobuffered_level0 <= (cdcusbphy_inhandler_syncfifobuffered_level0 - 1'd1); + end + end + if (cdcusbphy_inhandler_data_buf_reset) begin + cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0; + cdcusbphy_inhandler_syncfifobuffered_level0 <= 7'd0; + cdcusbphy_inhandler_syncfifobuffered_produce <= 6'd0; + cdcusbphy_inhandler_syncfifobuffered_consume <= 6'd0; + end + if (cdcusbphy_inhandler_packet_clear) begin + cdcusbphy_inhandler_packet_pending <= 1'd0; + end + if (cdcusbphy_inhandler_packet_trigger) begin + cdcusbphy_inhandler_packet_pending <= 1'd1; + end + if ((cdcusbphy_outhandler_csrfield_reset | cdcusbphy_outhandler_usb_reset)) begin + cdcusbphy_outhandler_stall_status <= 1'd0; + end else begin + if ((cdcusbphy_usb_core_setup | (cdcusbphy_outhandler_ctrl_re & (~cdcusbphy_outhandler_csrfield_stall)))) begin + cdcusbphy_outhandler_stall_status <= (cdcusbphy_outhandler_stall_status & (~cdcusbphy_outhandler_ep_mask)); + end else begin + if (cdcusbphy_outhandler_ctrl_re) begin + cdcusbphy_outhandler_stall_status <= (cdcusbphy_outhandler_stall_status | cdcusbphy_outhandler_ep_mask); + end + end + end + if (cdcusbphy_usb_core_poll) begin + cdcusbphy_outhandler_responding <= cdcusbphy_outhandler_response; + end + if (cdcusbphy_outhandler_csrfield_reset) begin + cdcusbphy_outhandler_enable_status <= 1'd0; + end else begin + if ((cdcusbphy_usb_core_commit & cdcusbphy_outhandler_responding)) begin + cdcusbphy_outhandler_epno <= cdcusbphy_usb_core_endp; + cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status & (~cdcusbphy_outhandler_ep_mask)); + cdcusbphy_outhandler_responding <= 1'd0; + end else begin + if (cdcusbphy_outhandler_ctrl_re) begin + if (cdcusbphy_outhandler_csrfield_enable) begin + cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status | cdcusbphy_outhandler_ep_mask); + end else begin + cdcusbphy_outhandler_enable_status <= (cdcusbphy_outhandler_enable_status & (~cdcusbphy_outhandler_ep_mask)); + end + end + end + end + if (cdcusbphy_outhandler_syncfifobuffered_syncfifo_re) begin + cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd1; + end else begin + if (cdcusbphy_outhandler_syncfifobuffered_re) begin + cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0; + end + end + if (((cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_outhandler_syncfifobuffered_replace))) begin + if ((cdcusbphy_outhandler_syncfifobuffered_produce == 7'd65)) begin + cdcusbphy_outhandler_syncfifobuffered_produce <= 1'd0; + end else begin + cdcusbphy_outhandler_syncfifobuffered_produce <= (cdcusbphy_outhandler_syncfifobuffered_produce + 1'd1); + end + end + if (cdcusbphy_outhandler_syncfifobuffered_do_read) begin + if ((cdcusbphy_outhandler_syncfifobuffered_consume == 7'd65)) begin + cdcusbphy_outhandler_syncfifobuffered_consume <= 1'd0; + end else begin + cdcusbphy_outhandler_syncfifobuffered_consume <= (cdcusbphy_outhandler_syncfifobuffered_consume + 1'd1); + end + end + if (((cdcusbphy_outhandler_syncfifobuffered_syncfifo_we & cdcusbphy_outhandler_syncfifobuffered_syncfifo_writable) & (~cdcusbphy_outhandler_syncfifobuffered_replace))) begin + if ((~cdcusbphy_outhandler_syncfifobuffered_do_read)) begin + cdcusbphy_outhandler_syncfifobuffered_level0 <= (cdcusbphy_outhandler_syncfifobuffered_level0 + 1'd1); + end + end else begin + if (cdcusbphy_outhandler_syncfifobuffered_do_read) begin + cdcusbphy_outhandler_syncfifobuffered_level0 <= (cdcusbphy_outhandler_syncfifobuffered_level0 - 1'd1); + end + end + if (cdcusbphy_outhandler_data_buf_reset) begin + cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0; + cdcusbphy_outhandler_syncfifobuffered_level0 <= 7'd0; + cdcusbphy_outhandler_syncfifobuffered_produce <= 7'd0; + cdcusbphy_outhandler_syncfifobuffered_consume <= 7'd0; + end + if (cdcusbphy_outhandler_packet_clear) begin + cdcusbphy_outhandler_packet_pending <= 1'd0; + end + if (cdcusbphy_outhandler_packet_trigger) begin + cdcusbphy_outhandler_packet_pending <= 1'd1; + end + subfragments_clockdomainsrenamer_state1 <= subfragments_clockdomainsrenamer_next_state1; + if (cdcusbphy_usb_core_addr_csrtransform_next_value_ce) begin + cdcusbphy_usb_core_addr <= cdcusbphy_usb_core_addr_csrtransform_next_value; + end + if (cdcusbphy_resetinserter_reset) begin + cdcusbphy_usb_core_addr <= 7'd0; + subfragments_clockdomainsrenamer_state1 <= 3'd0; + end + if ((cdcusbphy_dtr & (cdcusbphy_configured_delay > 1'd0))) begin + cdcusbphy_configured_delay <= (cdcusbphy_configured_delay - 1'd1); + end else begin + if (cdcusbphy_configure_set) begin + cdcusbphy_configured_delay <= 1'd0; + end + end + cdcusbphy_pullup_re <= cdcusbphy_csrtransform_pullup_out_re; + if (cdcusbphy_csrtransform_pullup_out_re) begin + cdcusbphy_pullup_storage <= cdcusbphy_csrtransform; + end + cdcusbphy_csrstorage_re <= cdcusbphy_csrtransform_address_re; + if (cdcusbphy_csrtransform_address_re) begin + cdcusbphy_csrstorage_storage[6:0] <= cdcusbphy_csrtransform_address_addr0; + end + if (cdcusbphy_address_reset) begin + cdcusbphy_csrstorage_storage <= 7'd0; + cdcusbphy_csrstorage_re <= 1'd0; + end + cdcusbphy_setuphandler_ctrl_re <= cdcusbphy_csrtransform_setup_ctrl_re; + if (cdcusbphy_csrtransform_setup_ctrl_re) begin + cdcusbphy_setuphandler_ctrl_storage[5] <= cdcusbphy_csrtransform_setup_ctrl_reset0; + end + cdcusbphy_setuphandler_eventmanager_enable_re <= cdcusbphy_csrtransform_setup_ev_enable_re; + if (cdcusbphy_csrtransform_setup_ev_enable_re) begin + cdcusbphy_setuphandler_eventmanager_enable_storage[0] <= cdcusbphy_csrtransform_setup_ev_enable_ready0; + end + if (cdcusbphy_csrtransform_setup_ev_enable_re) begin + cdcusbphy_setuphandler_eventmanager_enable_storage[1] <= cdcusbphy_csrtransform_setup_ev_enable_reset0; + end + cdcusbphy_inhandler_data_re <= cdcusbphy_csrtransform_in_data_re; + if (cdcusbphy_csrtransform_in_data_re) begin + cdcusbphy_inhandler_data_storage[7:0] <= cdcusbphy_csrtransform_in_data_data0; + end + cdcusbphy_inhandler_ctrl_re <= cdcusbphy_csrtransform_in_ctrl_re; + if (cdcusbphy_csrtransform_in_ctrl_re) begin + cdcusbphy_inhandler_ctrl_storage[3:0] <= cdcusbphy_csrtransform_in_ctrl_epno0; + end + if (cdcusbphy_csrtransform_in_ctrl_re) begin + cdcusbphy_inhandler_ctrl_storage[5] <= cdcusbphy_csrtransform_in_ctrl_reset0; + end + if (cdcusbphy_csrtransform_in_ctrl_re) begin + cdcusbphy_inhandler_ctrl_storage[6] <= cdcusbphy_csrtransform_in_ctrl_stall0; + end + cdcusbphy_inhandler_enable_re <= cdcusbphy_csrtransform_in_ev_enable_re; + if (cdcusbphy_csrtransform_in_ev_enable_re) begin + cdcusbphy_inhandler_enable_storage <= cdcusbphy_csrtransform_in_ev_enable_done0; + end + cdcusbphy_outhandler_ctrl_re <= cdcusbphy_csrtransform_out_ctrl_re; + if (cdcusbphy_csrtransform_out_ctrl_re) begin + cdcusbphy_outhandler_ctrl_storage[3:0] <= cdcusbphy_csrtransform_out_ctrl_epno0; + end + if (cdcusbphy_csrtransform_out_ctrl_re) begin + cdcusbphy_outhandler_ctrl_storage[4] <= cdcusbphy_csrtransform_out_ctrl_enable0; + end + if (cdcusbphy_csrtransform_out_ctrl_re) begin + cdcusbphy_outhandler_ctrl_storage[5] <= cdcusbphy_csrtransform_out_ctrl_reset0; + end + if (cdcusbphy_csrtransform_out_ctrl_re) begin + cdcusbphy_outhandler_ctrl_storage[6] <= cdcusbphy_csrtransform_out_ctrl_stall0; + end + cdcusbphy_outhandler_enable_re <= cdcusbphy_csrtransform_out_ev_enable_re; + if (cdcusbphy_csrtransform_out_ev_enable_re) begin + cdcusbphy_outhandler_enable_storage <= cdcusbphy_csrtransform_out_ev_enable_done0; + end + if (cdcusbphy_usb_core_usb_reset) begin + cdcusbphy_in_next <= 1'd0; + cdcusbphy_out_next <= 1'd0; + end else begin + if ((cdcusbphy_inhandler_packet_pending & (~cdcusbphy_outhandler_packet_pending))) begin + cdcusbphy_in_next <= 1'd1; + cdcusbphy_out_next <= 1'd0; + end else begin + if (((~cdcusbphy_inhandler_packet_pending) & cdcusbphy_outhandler_packet_pending)) begin + cdcusbphy_in_next <= 1'd0; + cdcusbphy_out_next <= 1'd1; + end else begin + if (((~cdcusbphy_inhandler_packet_pending) & (~cdcusbphy_outhandler_packet_pending))) begin + cdcusbphy_in_next <= 1'd0; + cdcusbphy_out_next <= 1'd0; + end + end + end + end + if (cdcusbphy_debug_bridge_wishbone_ack) begin + cdcusbphy_debug_bridge_rd_data <= cdcusbphy_debug_bridge_wishbone_dat_r; + end + subfragments_state <= subfragments_next_state; + if (cdcusbphy_setup_index_fsm_next_value_ce0) begin + cdcusbphy_setup_index <= cdcusbphy_setup_index_fsm_next_value0; + end + if (cdcusbphy_delayed_re_fsm_next_value_ce1) begin + cdcusbphy_delayed_re <= cdcusbphy_delayed_re_fsm_next_value1; + end + if (cdcusbphy_data_d1_fsm_t_next_value_ce0) begin + cdcusbphy_data_d1 <= cdcusbphy_data_d1_fsm_t_next_value0; + end + if (cdcusbphy_data_d2_fsm_t_next_value_ce1) begin + cdcusbphy_data_d2 <= cdcusbphy_data_d2_fsm_t_next_value1; + end + if (cdcusbphy_re_d1_fsm_t_next_value_ce2) begin + cdcusbphy_re_d1 <= cdcusbphy_re_d1_fsm_t_next_value2; + end + if (cdcusbphy_re_d2_fsm_t_next_value_ce3) begin + cdcusbphy_re_d2 <= cdcusbphy_re_d2_fsm_t_next_value3; + end + if (cdcusbphy_usbPacket_fsm_cases_next_value_ce0) begin + cdcusbphy_usbPacket <= cdcusbphy_usbPacket_fsm_cases_next_value0; + end + if (cdcusbphy_wLength_fsm_cases_next_value_ce1) begin + cdcusbphy_wLength <= cdcusbphy_wLength_fsm_cases_next_value1; + end + if (cdcusbphy_new_address_fsm_t_next_value_ce4) begin + cdcusbphy_new_address <= cdcusbphy_new_address_fsm_t_next_value4; + end + if (cdcusbphy_rts_fsm_t_next_value_ce5) begin + cdcusbphy_rts <= cdcusbphy_rts_fsm_t_next_value5; + end + if (cdcusbphy_dtr_fsm_t_next_value_ce6) begin + cdcusbphy_dtr <= cdcusbphy_dtr_fsm_t_next_value6; + end + if (cdcusbphy_bytes_remaining_fsm_f_next_value_ce0) begin + cdcusbphy_bytes_remaining <= cdcusbphy_bytes_remaining_fsm_f_next_value0; + end + if (cdcusbphy_bytes_addr_fsm_f_next_value_ce1) begin + cdcusbphy_bytes_addr <= cdcusbphy_bytes_addr_fsm_f_next_value1; + end + toggle_o_r <= toggle_o; + asyncfifo0_graycounter1_q_binary <= asyncfifo0_graycounter1_q_next_binary; + asyncfifo0_graycounter1_q <= asyncfifo0_graycounter1_q_next; + asyncfifo1_graycounter2_q_binary <= asyncfifo1_graycounter2_q_next_binary; + asyncfifo1_graycounter2_q <= asyncfifo1_graycounter2_q_next; + if (usb_12_rst) begin + cdcusbphy_usb_core_tx_i_oe <= 1'd0; + cdcusbphy_usb_core_tx_shifter_o_get <= 1'd0; + cdcusbphy_usb_core_tx_shifter_shifter <= 8'd0; + cdcusbphy_usb_core_tx_shifter_pos <= 8'd1; + cdcusbphy_usb_core_tx_bitstuff_o_data <= 1'd0; + cdcusbphy_usb_core_tx_sync_pulse <= 8'd0; + cdcusbphy_usb_core_tx_bitstuff_valid_data <= 1'd0; + cdcusbphy_usb_core_tx_state_gray <= 2'd0; + cdcusbphy_usb_core_txstate_pid <= 4'd0; + cdcusbphy_usb_core_txstate_crc_cur <= 16'd65535; + cdcusbphy_usb_core_rx_o_pkt_in_progress <= 1'd0; + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q <= 2'd0; + cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q_binary <= 2'd0; + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q <= 2'd0; + cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q_binary <= 2'd0; + cdcusbphy_usb_core_o_pid <= 4'd0; + cdcusbphy_usb_core_o_addr <= 7'd0; + cdcusbphy_usb_core_endp4 <= 1'd0; + cdcusbphy_usb_core_o_endp <= 4'd0; + cdcusbphy_usb_core_crc5 <= 5'd0; + cdcusbphy_usb_core_addr <= 7'd0; + cdcusbphy_usb_core_tok <= 4'd0; + cdcusbphy_usb_core_endp <= 4'd0; + cdcusbphy_usb_core_response_pid <= 4'd0; + cdcusbphy_pullup_storage <= 1'd0; + cdcusbphy_pullup_re <= 1'd0; + cdcusbphy_csrstorage_storage <= 7'd0; + cdcusbphy_csrstorage_re <= 1'd0; + cdcusbphy_setuphandler_epno <= 1'd0; + cdcusbphy_setuphandler_ctrl_storage <= 6'd0; + cdcusbphy_setuphandler_ctrl_re <= 1'd0; + cdcusbphy_setuphandler_packet_pending <= 1'd0; + cdcusbphy_setuphandler_reset_pending <= 1'd0; + cdcusbphy_setuphandler_reset_trigger_d <= 1'd0; + cdcusbphy_setuphandler_eventmanager_enable_storage <= 2'd0; + cdcusbphy_setuphandler_eventmanager_enable_re <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_readable <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_level0 <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_produce <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_consume <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_data_byte <= 4'd0; + cdcusbphy_setuphandler_setuphandlerinner_have_data_stage <= 1'd0; + cdcusbphy_setuphandler_setuphandlerinner_is_in <= 1'd0; + cdcusbphy_inhandler_dtbs <= 16'd1; + cdcusbphy_inhandler_stall_status <= 16'd0; + cdcusbphy_inhandler_syncfifobuffered_readable <= 1'd0; + cdcusbphy_inhandler_syncfifobuffered_level0 <= 7'd0; + cdcusbphy_inhandler_syncfifobuffered_produce <= 6'd0; + cdcusbphy_inhandler_syncfifobuffered_consume <= 6'd0; + cdcusbphy_inhandler_data_storage <= 8'd0; + cdcusbphy_inhandler_data_re <= 1'd0; + cdcusbphy_inhandler_ctrl_storage <= 7'd0; + cdcusbphy_inhandler_ctrl_re <= 1'd0; + cdcusbphy_inhandler_packet_pending <= 1'd0; + cdcusbphy_inhandler_enable_storage <= 1'd0; + cdcusbphy_inhandler_enable_re <= 1'd0; + cdcusbphy_inhandler_queued <= 1'd0; + cdcusbphy_inhandler_was_queued <= 1'd0; + cdcusbphy_inhandler_transmitted <= 1'd0; + cdcusbphy_outhandler_syncfifobuffered_readable <= 1'd0; + cdcusbphy_outhandler_syncfifobuffered_level0 <= 7'd0; + cdcusbphy_outhandler_syncfifobuffered_produce <= 7'd0; + cdcusbphy_outhandler_syncfifobuffered_consume <= 7'd0; + cdcusbphy_outhandler_ctrl_storage <= 7'd0; + cdcusbphy_outhandler_ctrl_re <= 1'd0; + cdcusbphy_outhandler_packet_pending <= 1'd0; + cdcusbphy_outhandler_enable_storage <= 1'd0; + cdcusbphy_outhandler_enable_re <= 1'd0; + cdcusbphy_outhandler_stall_status <= 16'd0; + cdcusbphy_outhandler_enable_status <= 16'd0; + cdcusbphy_outhandler_epno <= 4'd0; + cdcusbphy_outhandler_responding <= 1'd0; + cdcusbphy_in_next <= 1'd0; + cdcusbphy_out_next <= 1'd0; + cdcusbphy_rts <= 1'd0; + cdcusbphy_dtr <= 1'd0; + cdcusbphy_bytes_remaining <= 6'd0; + cdcusbphy_bytes_addr <= 9'd0; + cdcusbphy_new_address <= 7'd0; + cdcusbphy_configured_delay <= 16'd65535; + cdcusbphy_usbPacket <= 32'd0; + cdcusbphy_wLength <= 8'd0; + cdcusbphy_setup_index <= 4'd0; + cdcusbphy_delayed_re <= 1'd0; + cdcusbphy_data_d1 <= 8'd0; + cdcusbphy_re_d1 <= 1'd0; + cdcusbphy_data_d2 <= 8'd0; + cdcusbphy_re_d2 <= 1'd0; + asyncfifo0_graycounter1_q <= 3'd0; + asyncfifo0_graycounter1_q_binary <= 3'd0; + asyncfifo1_graycounter2_q <= 3'd0; + asyncfifo1_graycounter2_q_binary <= 3'd0; + subfragments_fsm_state <= 2'd0; + subfragments_resetinserter_state <= 3'd0; + subfragments_txpacketsend_state <= 4'd0; + subfragments_packetheaderdecode_state <= 3'd0; + subfragments_clockdomainsrenamer_state0 <= 4'd1; + subfragments_usbwishbonebridge_state <= 4'd0; + subfragments_clockdomainsrenamer_state1 <= 3'd0; + subfragments_state <= 3'd0; + end + multiregimpl2_regs <= cdcusbphy_usb_core_tx_o_oe; + multiregimpl3_regs0 <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q; + multiregimpl3_regs1 <= multiregimpl3_regs0; + multiregimpl5_regs0 <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q; + multiregimpl5_regs1 <= multiregimpl5_regs0; + multiregimpl9_regs0 <= toggle_i; + multiregimpl9_regs1 <= multiregimpl9_regs0; + multiregimpl10_regs0 <= asyncfifo0_graycounter0_q; + multiregimpl10_regs1 <= multiregimpl10_regs0; + multiregimpl13_regs0 <= asyncfifo1_graycounter3_q; + multiregimpl13_regs1 <= multiregimpl13_regs0; +end + +always @(posedge usb_48_clk) begin + cdcusbphy_usb_core_tx_nrzi_o_oe <= cdcusbphy_usb_core_tx_nrzi_oe0; + cdcusbphy_usb_core_tx_nrzi_o_usbp <= cdcusbphy_usb_core_tx_nrzi_usbp; + cdcusbphy_usb_core_tx_nrzi_o_usbn <= cdcusbphy_usb_core_tx_nrzi_usbn; + subfragments_txnrziencoder_state <= subfragments_txnrziencoder_next_state; + if (cdcusbphy_usb_core_rx_line_state_valid) begin + if (cdcusbphy_usb_core_rx_line_state_se01) begin + if ((~cdcusbphy_usb_core_rx_reset_counter[6])) begin + cdcusbphy_usb_core_rx_reset_counter <= (cdcusbphy_usb_core_rx_reset_counter + 1'd1); + end + end else begin + cdcusbphy_usb_core_rx_reset_counter <= 1'd0; + end + end + cdcusbphy_usb_core_rx_last_reset <= cdcusbphy_usb_core_rx_reset1; + cdcusbphy_usb_core_rx_line_state_valid <= (cdcusbphy_usb_core_rx_line_state_phase == 1'd1); + if (cdcusbphy_usb_core_rx_line_state_dt) begin + cdcusbphy_usb_core_rx_line_state_phase <= 1'd0; + cdcusbphy_usb_core_rx_line_state_valid <= 1'd0; + end else begin + cdcusbphy_usb_core_rx_line_state_phase <= (cdcusbphy_usb_core_rx_line_state_phase + 1'd1); + end + cdcusbphy_usb_core_rx_line_state_dj1 <= cdcusbphy_usb_core_rx_line_state_dj0; + cdcusbphy_usb_core_rx_line_state_dk1 <= cdcusbphy_usb_core_rx_line_state_dk0; + cdcusbphy_usb_core_rx_line_state_se01 <= cdcusbphy_usb_core_rx_line_state_se00; + cdcusbphy_usb_core_rx_line_state_se11 <= cdcusbphy_usb_core_rx_line_state_se10; + subfragments_rxpipeline_state <= subfragments_rxpipeline_next_state; + if (cdcusbphy_usb_core_rx_nrzi_i_valid) begin + cdcusbphy_usb_core_rx_nrzi_last_data <= cdcusbphy_usb_core_rx_nrzi_i_dk; + cdcusbphy_usb_core_rx_nrzi_o_data <= (~(cdcusbphy_usb_core_rx_nrzi_i_dk ^ cdcusbphy_usb_core_rx_nrzi_last_data)); + cdcusbphy_usb_core_rx_nrzi_o_se0 <= ((~cdcusbphy_usb_core_rx_nrzi_i_dj) & (~cdcusbphy_usb_core_rx_nrzi_i_dk)); + end + cdcusbphy_usb_core_rx_nrzi_o_valid <= cdcusbphy_usb_core_rx_nrzi_i_valid; + subfragments_rxpipeline_rxpacketdetect_state <= subfragments_rxpipeline_rxpacketdetect_next_state; + if (cdcusbphy_usb_core_rx_detect_reset) begin + subfragments_rxpipeline_rxpacketdetect_state <= 3'd0; + end + cdcusbphy_usb_core_rx_bitstuff_o_data <= cdcusbphy_usb_core_rx_bitstuff_i_data; + cdcusbphy_usb_core_rx_bitstuff_o_stall <= (cdcusbphy_usb_core_rx_bitstuff_drop_bit | (~cdcusbphy_usb_core_rx_bitstuff_i_valid)); + cdcusbphy_usb_core_rx_bitstuff_o_error <= ((cdcusbphy_usb_core_rx_bitstuff_drop_bit & cdcusbphy_usb_core_rx_bitstuff_i_data) & cdcusbphy_usb_core_rx_bitstuff_i_valid); + subfragments_rxpipeline_rxbitstuffremover_state <= subfragments_rxpipeline_rxbitstuffremover_next_state; + if (cdcusbphy_usb_core_rx_bitstuff_reset) begin + cdcusbphy_usb_core_rx_bitstuff_o_data <= 1'd0; + cdcusbphy_usb_core_rx_bitstuff_o_error <= 1'd0; + cdcusbphy_usb_core_rx_bitstuff_o_stall <= 1'd1; + subfragments_rxpipeline_rxbitstuffremover_state <= 3'd0; + end + cdcusbphy_usb_core_rx_shifter_o_put <= ((cdcusbphy_usb_core_rx_shifter_shift_reg[7] & (~cdcusbphy_usb_core_rx_shifter_shift_reg[8])) & cdcusbphy_usb_core_rx_shifter_i_valid); + if (cdcusbphy_usb_core_rx_shifter_i_valid) begin + if (cdcusbphy_usb_core_rx_shifter_shift_reg[8]) begin + cdcusbphy_usb_core_rx_shifter_shift_reg <= {slice_proxy[7:0], cdcusbphy_usb_core_rx_shifter_i_data}; + end else begin + cdcusbphy_usb_core_rx_shifter_shift_reg <= {cdcusbphy_usb_core_rx_shifter_shift_reg[7:0], cdcusbphy_usb_core_rx_shifter_i_data}; + end + end + if (cdcusbphy_usb_core_rx_shifter_reset) begin + cdcusbphy_usb_core_rx_shifter_o_put <= 1'd0; + cdcusbphy_usb_core_rx_shifter_shift_reg <= 9'd1; + end + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next_binary; + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q <= cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_next; + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next_binary; + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q <= cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_next; + if (usb_48_rst) begin + cdcusbphy_usb_core_tx_nrzi_o_usbp <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_o_usbn <= 1'd0; + cdcusbphy_usb_core_tx_nrzi_o_oe <= 1'd0; + cdcusbphy_usb_core_rx_line_state_phase <= 2'd0; + cdcusbphy_usb_core_rx_line_state_valid <= 1'd0; + cdcusbphy_usb_core_rx_line_state_dj1 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_dk1 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_se01 <= 1'd0; + cdcusbphy_usb_core_rx_line_state_se11 <= 1'd0; + cdcusbphy_usb_core_rx_reset_counter <= 7'd0; + cdcusbphy_usb_core_rx_nrzi_o_valid <= 1'd0; + cdcusbphy_usb_core_rx_nrzi_o_data <= 1'd0; + cdcusbphy_usb_core_rx_nrzi_o_se0 <= 1'd0; + cdcusbphy_usb_core_rx_nrzi_last_data <= 1'd0; + cdcusbphy_usb_core_rx_bitstuff_o_data <= 1'd0; + cdcusbphy_usb_core_rx_bitstuff_o_error <= 1'd0; + cdcusbphy_usb_core_rx_bitstuff_o_stall <= 1'd1; + cdcusbphy_usb_core_rx_last_reset <= 1'd0; + cdcusbphy_usb_core_rx_shifter_o_put <= 1'd0; + cdcusbphy_usb_core_rx_shifter_shift_reg <= 9'd1; + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q <= 2'd0; + cdcusbphy_usb_core_rx_payloadFifo_graycounter0_q_binary <= 2'd0; + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q <= 2'd0; + cdcusbphy_usb_core_rx_flagsFifo_graycounter0_q_binary <= 2'd0; + subfragments_txnrziencoder_state <= 3'd0; + subfragments_rxpipeline_state <= 3'd0; + subfragments_rxpipeline_rxpacketdetect_state <= 3'd0; + subfragments_rxpipeline_rxbitstuffremover_state <= 3'd0; + end + multiregimpl0_regs0 <= cdcusbphy_usb_core_tx_fit_dat; + multiregimpl0_regs1 <= multiregimpl0_regs0; + multiregimpl0_regs2 <= multiregimpl0_regs1; + multiregimpl1_regs0 <= cdcusbphy_usb_core_tx_fit_oe; + multiregimpl1_regs1 <= multiregimpl1_regs0; + multiregimpl1_regs2 <= multiregimpl1_regs1; + multiregimpl4_regs0 <= cdcusbphy_usb_core_rx_payloadFifo_graycounter1_q; + multiregimpl4_regs1 <= multiregimpl4_regs0; + multiregimpl6_regs0 <= cdcusbphy_usb_core_rx_flagsFifo_graycounter1_q; + multiregimpl6_regs1 <= multiregimpl6_regs0; +end + +always @(posedge usb_48_to_12_clk) begin + crg_clk12_counter <= (crg_clk12_counter + 1'd1); + if (usb_48_to_12_rst) begin + crg_clk12_counter <= 2'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 2-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8 +// Port 1 | Read: Sync | Write: ---- | +reg [7:0] storage[0:1]; +reg [7:0] storage_dat0; +reg [7:0] storage_dat1; +always @(posedge usb_48_clk) begin + if (cdcusbphy_usb_core_rx_payloadFifo_wrport_we) + storage[cdcusbphy_usb_core_rx_payloadFifo_wrport_adr] <= cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_w; + storage_dat0 <= storage[cdcusbphy_usb_core_rx_payloadFifo_wrport_adr]; +end +always @(posedge usb_12_clk) begin + storage_dat1 <= storage[cdcusbphy_usb_core_rx_payloadFifo_rdport_adr]; +end +assign cdcusbphy_usb_core_rx_payloadFifo_wrport_dat_r = storage_dat0; +assign cdcusbphy_usb_core_rx_payloadFifo_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 2-words x 2-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 2 +// Port 1 | Read: Sync | Write: ---- | +reg [1:0] storage_1[0:1]; +reg [1:0] storage_1_dat0; +reg [1:0] storage_1_dat1; +always @(posedge usb_48_clk) begin + if (cdcusbphy_usb_core_rx_flagsFifo_wrport_we) + storage_1[cdcusbphy_usb_core_rx_flagsFifo_wrport_adr] <= cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_w; + storage_1_dat0 <= storage_1[cdcusbphy_usb_core_rx_flagsFifo_wrport_adr]; +end +always @(posedge usb_12_clk) begin + storage_1_dat1 <= storage_1[cdcusbphy_usb_core_rx_flagsFifo_rdport_adr]; +end +assign cdcusbphy_usb_core_rx_flagsFifo_wrport_dat_r = storage_1_dat0; +assign cdcusbphy_usb_core_rx_flagsFifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 10-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8 +// Port 1 | Read: Sync | Write: ---- | +reg [7:0] storage_2[0:9]; +reg [7:0] storage_2_dat0; +reg [7:0] storage_2_dat1; +always @(posedge usb_12_clk) begin + if (cdcusbphy_setuphandler_setuphandlerinner_wrport_we) + storage_2[cdcusbphy_setuphandler_setuphandlerinner_wrport_adr] <= cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_w; + storage_2_dat0 <= storage_2[cdcusbphy_setuphandler_setuphandlerinner_wrport_adr]; +end +always @(posedge usb_12_clk) begin + if (cdcusbphy_setuphandler_setuphandlerinner_rdport_re) + storage_2_dat1 <= storage_2[cdcusbphy_setuphandler_setuphandlerinner_rdport_adr]; +end +assign cdcusbphy_setuphandler_setuphandlerinner_wrport_dat_r = storage_2_dat0; +assign cdcusbphy_setuphandler_setuphandlerinner_rdport_dat_r = storage_2_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 64-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8 +// Port 1 | Read: Sync | Write: ---- | +reg [7:0] storage_3[0:63]; +reg [7:0] storage_3_dat0; +reg [7:0] storage_3_dat1; +always @(posedge usb_12_clk) begin + if (cdcusbphy_inhandler_syncfifobuffered_wrport_we) + storage_3[cdcusbphy_inhandler_syncfifobuffered_wrport_adr] <= cdcusbphy_inhandler_syncfifobuffered_wrport_dat_w; + storage_3_dat0 <= storage_3[cdcusbphy_inhandler_syncfifobuffered_wrport_adr]; +end +always @(posedge usb_12_clk) begin + if (cdcusbphy_inhandler_syncfifobuffered_rdport_re) + storage_3_dat1 <= storage_3[cdcusbphy_inhandler_syncfifobuffered_rdport_adr]; +end +assign cdcusbphy_inhandler_syncfifobuffered_wrport_dat_r = storage_3_dat0; +assign cdcusbphy_inhandler_syncfifobuffered_rdport_dat_r = storage_3_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_4: 66-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 8 +// Port 1 | Read: Sync | Write: ---- | +reg [7:0] storage_4[0:65]; +reg [7:0] storage_4_dat0; +reg [7:0] storage_4_dat1; +always @(posedge usb_12_clk) begin + if (cdcusbphy_outhandler_syncfifobuffered_wrport_we) + storage_4[cdcusbphy_outhandler_syncfifobuffered_wrport_adr] <= cdcusbphy_outhandler_syncfifobuffered_wrport_dat_w; + storage_4_dat0 <= storage_4[cdcusbphy_outhandler_syncfifobuffered_wrport_adr]; +end +always @(posedge usb_12_clk) begin + if (cdcusbphy_outhandler_syncfifobuffered_rdport_re) + storage_4_dat1 <= storage_4[cdcusbphy_outhandler_syncfifobuffered_rdport_adr]; +end +assign cdcusbphy_outhandler_syncfifobuffered_wrport_dat_r = storage_4_dat0; +assign cdcusbphy_outhandler_syncfifobuffered_rdport_dat_r = storage_4_dat1; + + +//------------------------------------------------------------------------------ +// Memory out_buffer: 249-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [7:0] out_buffer[0:248]; +initial begin + $readmemh("out_buffer.init", out_buffer); +end +reg [7:0] out_buffer_adr0; +always @(posedge usb_12_clk) begin + out_buffer_adr0 <= cdcusbphy_adr; +end +assign cdcusbphy_dat_r = out_buffer[out_buffer_adr0]; + + +//------------------------------------------------------------------------------ +// Memory storage_5: 4-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_5[0:3]; +reg [9:0] storage_5_dat0; +reg [9:0] storage_5_dat1; +always @(posedge sys_clk) begin + if (asyncfifo0_wrport_we) + storage_5[asyncfifo0_wrport_adr] <= asyncfifo0_wrport_dat_w; + storage_5_dat0 <= storage_5[asyncfifo0_wrport_adr]; +end +always @(posedge usb_12_clk) begin + storage_5_dat1 <= storage_5[asyncfifo0_rdport_adr]; +end +assign asyncfifo0_wrport_dat_r = storage_5_dat0; +assign asyncfifo0_rdport_dat_r = storage_5_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_6: 4-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_6[0:3]; +reg [9:0] storage_6_dat0; +reg [9:0] storage_6_dat1; +always @(posedge usb_12_clk) begin + if (asyncfifo1_wrport_we) + storage_6[asyncfifo1_wrport_adr] <= asyncfifo1_wrport_dat_w; + storage_6_dat0 <= storage_6[asyncfifo1_wrport_adr]; +end +always @(posedge sys_clk) begin + storage_6_dat1 <= storage_6[asyncfifo1_rdport_adr]; +end +assign asyncfifo1_wrport_dat_r = storage_6_dat0; +assign asyncfifo1_rdport_dat_r = storage_6_dat1; + + +OFS1P3BX OFS1P3BX( + .D(usb_iobuf_usb_p_tx), + .PD(1'd0), + .SCLK(usb_48_clk), + .SP(1'd1), + .Q(inferedsdrtristate0__o) +); + +IFS1P3BX IFS1P3BX( + .D(inferedsdrtristate0__i), + .PD(1'd0), + .SCLK(usb_48_clk), + .SP(1'd1), + .Q(usb_iobuf_usb_p_t_i) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO ( + .B(usb_d_p), + .I(inferedsdrtristate0__o), + .T((~inferedsdrtristate0_oe)), + .O(inferedsdrtristate0__i) +); + +OFS1P3BX OFS1P3BX_1( + .D(usb_iobuf_usb_n_tx), + .PD(1'd0), + .SCLK(usb_48_clk), + .SP(1'd1), + .Q(inferedsdrtristate1__o) +); + +IFS1P3BX IFS1P3BX_1( + .D(inferedsdrtristate1__i), + .PD(1'd0), + .SCLK(usb_48_clk), + .SP(1'd1), + .Q(usb_iobuf_usb_n_t_i) +); + +TRELLIS_IO #( + .DIR("BIDIR") +) TRELLIS_IO_1 ( + .B(usb_d_n), + .I(inferedsdrtristate1__o), + .T((~inferedsdrtristate1_oe)), + .O(inferedsdrtristate1__i) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-02-07 17:23:11. +//------------------------------------------------------------------------------ diff --git a/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.ys b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.ys new file mode 100644 index 0000000..2e64865 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.ys @@ -0,0 +1,6 @@ +verilog_defaults -push +verilog_defaults -add -defer +read_verilog /home/matt/3rd/fpga/microwatt/valentyusb/generated/orangecrab-85-0.2/gateware/valentyusb.v +verilog_defaults -pop +attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 +synth_ecp5 -json valentyusb.json -top valentyusb \ No newline at end of file diff --git a/valentyusb/generated/orangecrab-85-0.2/software/include/generated/csr.h b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/csr.h new file mode 100644 index 0000000..5489474 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/csr.h @@ -0,0 +1,232 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11 +//-------------------------------------------------------------------------------- +#include +#ifndef __GENERATED_CSR_H +#define __GENERATED_CSR_H +#include +#include +#ifndef CSR_ACCESSORS_DEFINED +#include +#endif /* ! CSR_ACCESSORS_DEFINED */ +#ifndef CSR_BASE +#define CSR_BASE 0x0L +#endif + +/* uart */ +#define CSR_UART_BASE (CSR_BASE + 0x0L) +#define CSR_UART_RXTX_ADDR (CSR_BASE + 0x0L) +#define CSR_UART_RXTX_SIZE 1 +static inline uint32_t uart_rxtx_read(void) { + return csr_read_simple(CSR_BASE + 0x0L); +} +static inline void uart_rxtx_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x0L); +} +#define CSR_UART_TXFULL_ADDR (CSR_BASE + 0x4L) +#define CSR_UART_TXFULL_SIZE 1 +static inline uint32_t uart_txfull_read(void) { + return csr_read_simple(CSR_BASE + 0x4L); +} +#define CSR_UART_RXEMPTY_ADDR (CSR_BASE + 0x8L) +#define CSR_UART_RXEMPTY_SIZE 1 +static inline uint32_t uart_rxempty_read(void) { + return csr_read_simple(CSR_BASE + 0x8L); +} +#define CSR_UART_EV_STATUS_ADDR (CSR_BASE + 0xcL) +#define CSR_UART_EV_STATUS_SIZE 1 +static inline uint32_t uart_ev_status_read(void) { + return csr_read_simple(CSR_BASE + 0xcL); +} +#define CSR_UART_EV_STATUS_TX_OFFSET 0 +#define CSR_UART_EV_STATUS_TX_SIZE 1 +static inline uint32_t uart_ev_status_tx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t uart_ev_status_tx_read(void) { + uint32_t word = uart_ev_status_read(); + return uart_ev_status_tx_extract(word); +} +#define CSR_UART_EV_STATUS_RX_OFFSET 1 +#define CSR_UART_EV_STATUS_RX_SIZE 1 +static inline uint32_t uart_ev_status_rx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t uart_ev_status_rx_read(void) { + uint32_t word = uart_ev_status_read(); + return uart_ev_status_rx_extract(word); +} +#define CSR_UART_EV_PENDING_ADDR (CSR_BASE + 0x10L) +#define CSR_UART_EV_PENDING_SIZE 1 +static inline uint32_t uart_ev_pending_read(void) { + return csr_read_simple(CSR_BASE + 0x10L); +} +static inline void uart_ev_pending_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x10L); +} +#define CSR_UART_EV_PENDING_TX_OFFSET 0 +#define CSR_UART_EV_PENDING_TX_SIZE 1 +static inline uint32_t uart_ev_pending_tx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t uart_ev_pending_tx_read(void) { + uint32_t word = uart_ev_pending_read(); + return uart_ev_pending_tx_extract(word); +} +static inline uint32_t uart_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void uart_ev_pending_tx_write(uint32_t plain_value) { + uint32_t oldword = uart_ev_pending_read(); + uint32_t newword = uart_ev_pending_tx_replace(oldword, plain_value); + uart_ev_pending_write(newword); +} +#define CSR_UART_EV_PENDING_RX_OFFSET 1 +#define CSR_UART_EV_PENDING_RX_SIZE 1 +static inline uint32_t uart_ev_pending_rx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t uart_ev_pending_rx_read(void) { + uint32_t word = uart_ev_pending_read(); + return uart_ev_pending_rx_extract(word); +} +static inline uint32_t uart_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ; +} +static inline void uart_ev_pending_rx_write(uint32_t plain_value) { + uint32_t oldword = uart_ev_pending_read(); + uint32_t newword = uart_ev_pending_rx_replace(oldword, plain_value); + uart_ev_pending_write(newword); +} +#define CSR_UART_EV_ENABLE_ADDR (CSR_BASE + 0x14L) +#define CSR_UART_EV_ENABLE_SIZE 1 +static inline uint32_t uart_ev_enable_read(void) { + return csr_read_simple(CSR_BASE + 0x14L); +} +static inline void uart_ev_enable_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x14L); +} +#define CSR_UART_EV_ENABLE_TX_OFFSET 0 +#define CSR_UART_EV_ENABLE_TX_SIZE 1 +static inline uint32_t uart_ev_enable_tx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t uart_ev_enable_tx_read(void) { + uint32_t word = uart_ev_enable_read(); + return uart_ev_enable_tx_extract(word); +} +static inline uint32_t uart_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void uart_ev_enable_tx_write(uint32_t plain_value) { + uint32_t oldword = uart_ev_enable_read(); + uint32_t newword = uart_ev_enable_tx_replace(oldword, plain_value); + uart_ev_enable_write(newword); +} +#define CSR_UART_EV_ENABLE_RX_OFFSET 1 +#define CSR_UART_EV_ENABLE_RX_SIZE 1 +static inline uint32_t uart_ev_enable_rx_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t uart_ev_enable_rx_read(void) { + uint32_t word = uart_ev_enable_read(); + return uart_ev_enable_rx_extract(word); +} +static inline uint32_t uart_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ; +} +static inline void uart_ev_enable_rx_write(uint32_t plain_value) { + uint32_t oldword = uart_ev_enable_read(); + uint32_t newword = uart_ev_enable_rx_replace(oldword, plain_value); + uart_ev_enable_write(newword); +} +#define CSR_UART_TUNING_WORD_ADDR (CSR_BASE + 0x18L) +#define CSR_UART_TUNING_WORD_SIZE 1 +static inline uint32_t uart_tuning_word_read(void) { + return csr_read_simple(CSR_BASE + 0x18L); +} +static inline void uart_tuning_word_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x18L); +} +#define CSR_UART_CONFIGURED_ADDR (CSR_BASE + 0x1cL) +#define CSR_UART_CONFIGURED_SIZE 1 +static inline uint32_t uart_configured_read(void) { + return csr_read_simple(CSR_BASE + 0x1cL); +} +static inline void uart_configured_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x1cL); +} + +/* ctrl */ +#define CSR_CTRL_BASE (CSR_BASE + 0x800L) +#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x800L) +#define CSR_CTRL_RESET_SIZE 1 +static inline uint32_t ctrl_reset_read(void) { + return csr_read_simple(CSR_BASE + 0x800L); +} +static inline void ctrl_reset_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x800L); +} +#define CSR_CTRL_RESET_SOC_RST_OFFSET 0 +#define CSR_CTRL_RESET_SOC_RST_SIZE 1 +static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 0) & mask ); +} +static inline uint32_t ctrl_reset_soc_rst_read(void) { + uint32_t word = ctrl_reset_read(); + return ctrl_reset_soc_rst_extract(word); +} +static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ; +} +static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) { + uint32_t oldword = ctrl_reset_read(); + uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value); + ctrl_reset_write(newword); +} +#define CSR_CTRL_RESET_CPU_RST_OFFSET 1 +#define CSR_CTRL_RESET_CPU_RST_SIZE 1 +static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) { + uint32_t mask = ((1 << 1)-1); + return ( (oldword >> 1) & mask ); +} +static inline uint32_t ctrl_reset_cpu_rst_read(void) { + uint32_t word = ctrl_reset_read(); + return ctrl_reset_cpu_rst_extract(word); +} +static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) { + uint32_t mask = ((1 << 1)-1); + return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ; +} +static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) { + uint32_t oldword = ctrl_reset_read(); + uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value); + ctrl_reset_write(newword); +} +#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x804L) +#define CSR_CTRL_SCRATCH_SIZE 1 +static inline uint32_t ctrl_scratch_read(void) { + return csr_read_simple(CSR_BASE + 0x804L); +} +static inline void ctrl_scratch_write(uint32_t v) { + csr_write_simple(v, CSR_BASE + 0x804L); +} +#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x808L) +#define CSR_CTRL_BUS_ERRORS_SIZE 1 +static inline uint32_t ctrl_bus_errors_read(void) { + return csr_read_simple(CSR_BASE + 0x808L); +} + +#endif diff --git a/valentyusb/generated/orangecrab-85-0.2/software/include/generated/git.h b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/git.h new file mode 100644 index 0000000..fb53565 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/git.h @@ -0,0 +1,9 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_GIT_H +#define __GENERATED_GIT_H + +#define MIGEN_GIT_SHA1 "--------" +#define LITEX_GIT_SHA1 "--------" +#endif diff --git a/valentyusb/generated/orangecrab-85-0.2/software/include/generated/mem.h b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/mem.h new file mode 100644 index 0000000..ce41a59 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/mem.h @@ -0,0 +1,15 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_MEM_H +#define __GENERATED_MEM_H + +#ifndef CSR_BASE +#define CSR_BASE 0x00000000L +#define CSR_SIZE 0x00010000 +#endif + +#ifndef MEM_REGIONS +#define MEM_REGIONS "CSR 0x00000000 0x10000 " +#endif +#endif diff --git a/valentyusb/generated/orangecrab-85-0.2/software/include/generated/soc.h b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/soc.h new file mode 100644 index 0000000..71a1271 --- /dev/null +++ b/valentyusb/generated/orangecrab-85-0.2/software/include/generated/soc.h @@ -0,0 +1,40 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (--------) & LiteX (--------) on 2022-02-07 17:23:11 +//-------------------------------------------------------------------------------- +#ifndef __GENERATED_SOC_H +#define __GENERATED_SOC_H +#define CONFIG_CLOCK_FREQUENCY 48000000 +#define CONFIG_CPU_TYPE_NONE +#define CONFIG_CPU_VARIANT_STANDARD +#define CONFIG_CPU_HUMAN_NAME "Unknown" +#define CONFIG_CSR_DATA_WIDTH 32 +#define CONFIG_CSR_ALIGNMENT 32 +#define CONFIG_BUS_STANDARD "WISHBONE" +#define CONFIG_BUS_DATA_WIDTH 32 +#define CONFIG_BUS_ADDRESS_WIDTH 32 + +#ifndef __ASSEMBLER__ +static inline int config_clock_frequency_read(void) { + return 48000000; +} +static inline const char * config_cpu_human_name_read(void) { + return "Unknown"; +} +static inline int config_csr_data_width_read(void) { + return 32; +} +static inline int config_csr_alignment_read(void) { + return 32; +} +static inline const char * config_bus_standard_read(void) { + return "WISHBONE"; +} +static inline int config_bus_data_width_read(void) { + return 32; +} +static inline int config_bus_address_width_read(void) { + return 32; +} +#endif // !__ASSEMBLER__ + +#endif -- 2.30.2