From 6bed1847c1bcdb9213c81b325ee9068a59257d6d Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Tue, 20 Sep 2022 00:47:09 +0300 Subject: [PATCH] power_insn: simplify branch table --- src/openpower/decoder/power_insn.py | 15 ++++++++------- src/openpower/sv/trans/svp64.py | 11 ++++++----- 2 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index edc103bd..5fc8f00c 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -1852,16 +1852,17 @@ class RM(BaseRM): search = ((int(rm.mode) << 1) | (regtype or 0)) elif record.svp64.mode is _SVMode.BRANCH: - # just mode 5-bit. could be reduced down to 2, oh well. - # mode mask member + # just mode 2-bit + # mode mask member table = ( - (0b00000, 0b11000, "simple"), # simple - (0b01000, 0b11000, "vls"), # VLset - (0b10000, 0b11000, "ctr"), # CTR mode - (0b11000, 0b11000, "ctrvls"), # CTR+VLset mode + (0b00, 0b11, "simple"), # simple + (0b01, 0b11, "vls"), # VLset + (0b10, 0b11, "ctr"), # CTR mode + (0b11, 0b11, "ctrvls"), # CTR+VLset mode ) # slightly weird: doesn't have a 5-bit "mode" field like others - search = int(rm[19:23]) + rm = rm.branch + search = int(rm.mode[0, 1]) # look up in table if table is not None: diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 5fab53d1..3b42951e 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -1365,11 +1365,12 @@ class SVP64Asm: # and subvl: bits 8-9 svp64_rm.subvl = subvl - # put in elwidths - # srcwid: bits 6-7 - svp64_rm.ewsrc = srcwid - # destwid: bits 4-5 - svp64_rm.elwidth = destwid + # put in elwidths unless bc + if not is_bc: + # srcwid: bits 6-7 + svp64_rm.ewsrc = srcwid + # destwid: bits 4-5 + svp64_rm.elwidth = destwid # nice debug printout. (and now for something completely different) # https://youtu.be/u0WOIwlXE9g?t=146 -- 2.30.2