From 6bf8508fdcc0909103090e2747584ac4596a204d Mon Sep 17 00:00:00 2001
From: Gabor Dozsa <gabor.dozsa@arm.com>
Date: Tue, 30 Apr 2019 10:20:40 +0100
Subject: [PATCH] x86: Mark translation as delayed in case of a hw page table
 walk

This information is used by the LSQ in the O3 cpu (since commit
"51becd2... cpu-o3: O3 LSQ Generalisation")

Change-Id: I35fe7e2f8428641d863af0e79e28b0b259fb0b00
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18508
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/x86/tlb.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 33de0583e..84965b881 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -443,6 +443,8 @@ TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
         TLB::translate(req, tc, translation, mode, delayedResponse, true);
     if (!delayedResponse)
         translation->finish(fault, req, tc, mode);
+    else
+        translation->markDelayed();
 }
 
 Walker *
-- 
2.30.2