From 6bfcd543eeaaea4d6d5e7224d0d813e9c2afc4e3 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sat, 2 Oct 2021 21:11:00 +0100 Subject: [PATCH] --- 3d_gpu/architecture/dynamic_simd.mdwn | 38 +++++++++++++-------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn index 3f426c967..92c223482 100644 --- a/3d_gpu/architecture/dynamic_simd.mdwn +++ b/3d_gpu/architecture/dynamic_simd.mdwn @@ -123,6 +123,25 @@ basic HDL is literally an order of magnitude larger: with m.ElIf(....) .... +# Rationale / Introduction + +To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed. + +Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed. + +Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs. Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results. + +Pages below describe the basic features of each and track the relevant bugreports. + +* [[dynamic_simd/eq]] aka `__eq__` not to be confused with nmigen eq +* [[dynamic_simd/assign]] nmigen eq (assignment) +* [[dynamic_simd/gt]] +* [[dynamic_simd/add]] +* [[dynamic_simd/cat]] - limited capability +* [[dynamic_simd/mul]] +* [[dynamic_simd/shift]] +* [[dynamic_simd/logicops]] some all xor bool + # Alternative implementation concepts Several alternative ideas have been proposed. They are listed here for @@ -208,25 +227,6 @@ Bottom line is that all the alternatives are really quite harmful, costly, and unmaintainable, and in some cases actively damage nmigen's reputation as a stable, useful and powerful HDL. -# Rationale / Introduction - -To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed. - -Instead a suite of "partition points" identical in fashion to the Aspex Microelectronics ASP (Array-String-Architecture) architecture is deployed. - -Basic principle: when all partition gates are open the ALU is subdivided into isolated and independent 8 bit SIMD ALUs. Whenever any one gate is opened, the relevant 8 bit "part-results" are chained together in a downstream cascade to create 16 bit, 32 bit, 64 bit and 128 bit compound results. - -Pages below describe the basic features of each and track the relevant bugreports. - -* [[dynamic_simd/eq]] aka `__eq__` not to be confused with nmigen eq -* [[dynamic_simd/assign]] nmigen eq (assignment) -* [[dynamic_simd/gt]] -* [[dynamic_simd/add]] -* [[dynamic_simd/cat]] - limited capability -* [[dynamic_simd/mul]] -* [[dynamic_simd/shift]] -* [[dynamic_simd/logicops]] some all xor - # Integration with nmigen Dynamic partitioning of signals is not enough on its own. Normal nmigen programs involve conditional decisions, that means if statements and switch statements. -- 2.30.2