From 6c04e43201cc4fa7b9c7aab593131a69020dbf59 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 24 Dec 2020 13:33:57 +0000 Subject: [PATCH] --- openpower/sv/overview.mdwn | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-) diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 20e7c3aff..975acd05e 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -143,4 +143,29 @@ The solution comes in terms of rethinking the definition of a Register File. Rh reg_t int_regfile[128]; // SV extends to 128 regs -Then, our simple loop, instead of accessing the array of 64 bits with a computed index, would access the appropriate element of the appropriate type. Thus we have a series of overlapping conceptual arrays that each start at what is traditionally thought of as "a register". +Then, our simple loop, instead of accessing the array of 64 bits with a computed index, would access the appropriate element of the appropriate type. Thus we have a series of overlapping conceptual arrays that each start at what is traditionally thought of as "a register". It then helps if we have a couple of routines: + + + get_polymorphed_reg(reg, bitwidth, offset): + reg_t res = 0; + if bitwidth == 8: + reg.b = int_regfile[reg].b[offset] + elif bitwidth == 16: + reg.s = int_regfile[reg].s[offset] + elif bitwidth == 32: + reg.i = int_regfile[reg].i[offset] + elif bitwidth == default: # 64 + reg.l = int_regfile[reg].l[offset] + return res + + set_polymorphed_reg(reg, bitwidth, offset, val): + if (!int_csr[reg].isvec): # scalar + int_regfile[reg].l[0] = val + elif bitwidth == 8: + int_regfile[reg].b[offset] = val + elif bitwidth == 16: + int_regfile[reg].s[offset] = val + elif bitwidth == 32: + int_regfile[reg].i[offset] = val + elif bitwidth == default: # 64 + int_regfile[reg].l[offset] = val -- 2.30.2