From 6c08997f6f621cc24ab60cc9f45c1ba990db09c8 Mon Sep 17 00:00:00 2001 From: lkcl Date: Sun, 24 Apr 2022 03:53:49 +0100 Subject: [PATCH] --- openpower/sv/biginteger.mdwn | 42 +++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn index 06ba3ff94..44f67f85d 100644 --- a/openpower/sv/biginteger.mdwn +++ b/openpower/sv/biginteger.mdwn @@ -44,15 +44,23 @@ fashion that is hidden from the user, behind a consistent, stable ISA API. |-------|-----|------|------|------|------| | EXT04 | RT | RA | RB | RC | XO | -For the Opcode map (XO Field) -see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357. -Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) which is -in `110010`. +The pseudocode for `madded RT, RA, RB, RC` is: -| 110000 | 110001 | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 | -| ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ | -| maddhd | maddhdu | madded | maddld | rsvd | rsvd | rsvd | rsvd | + prod[0:127] = (RA) * (RB) + sum[0:127] = EXTZ(RC) + prod + RT <- sum[64:127] + RS <- sum[0:63] # RS is either RC or RT+VL + +RC is zero-extended (not shifted), the 128-bit product added +to it; the lower half of that result stored in RT and the upper half +in RS. + +The differences here to `maddhdu` are that `maddhdu` stores the upper +half in RT, where `madded` stores the upper half in RS. There is no +equivalent to `maddld` because `maddld` performs sign-extension on RC. +As a Scalar Power ISA operation, like `lq` and `stq` RS=RT+1. +SVP64 overrides this behaviour. For SVP64 EXTRA register extension, the `RM-1P-3S-1D` format is used with the additional bit set for determining RS. @@ -74,20 +82,14 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical to RC extended to SVP64 numbering, including whether RC is set Scalar or Vector. -The pseudocode for `madded RT, RA, RB, RC` is: - - prod[0:127] = (RA) * (RB) - sum[0:127] = EXTZ(RC) + prod - RT <- sum[64:127] - RS <- sum[0:63] # RS is either RC or RT+VL - -RC is zero-extended (not shifted), the 128-bit product added -to it; the lower half of that result stored in RT and the upper half -in RS. +For the Opcode map (XO Field) +see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357. +Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) which is +in `110010`. -The differences here to `maddhdu` are that `maddhdu` stores the upper -half in RT, where `madded` stores the upper half in RS. There is no -equivalent to `maddld` because `maddld` performs sign-extension on RC. +| 110000 | 110001 | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 | +| ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ | +| maddhd | maddhdu | madded | maddld | rsvd | rsvd | rsvd | rsvd | # divqdu RT,EA,RB -- 2.30.2