From 6c4c96fd45c41b8de15db7df4e4c1fefd0f46ba3 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Sat, 20 Nov 2021 14:54:35 +0000
Subject: [PATCH]

---
 3d_gpu/architecture/regfile.mdwn | 1 +
 1 file changed, 1 insertion(+)

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 14c0ba0c3..5616a2025 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -19,6 +19,7 @@ Source code:
 * core.py: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;hb=HEAD>
 * priority picker: <https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/picker.py;hb=HEAD>
 * all function units: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/compunits/compunits.py;hb=HEAD>
+* ReservationStations2 <https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/concurrentunit.py;hb=HEAD>
 
 For a GPU, the FP and Integer registers need to be a massive 128 x 64-bit.
 
-- 
2.30.2