From 6c51abf53294cb95fd67ae0c8c72c3509cbfd60d Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Aug 2022 14:51:16 +0100 Subject: [PATCH] Revert "fix setvl. not setting CR0 properly" This reverts commit f48aefa37b06a398e953ce3bd877d7b2bbfb6213. the approach of explicitly setting CR0 in pseudocode is not ok. ISACaller.handle_comparison is the correct place to do it - and i am not certain that there are special-cases needed (unlike svstep) --- openpower/isa/simplev.mdwn | 12 +----------- src/openpower/decoder/isa/caller.py | 2 +- 2 files changed, 2 insertions(+), 12 deletions(-) diff --git a/openpower/isa/simplev.mdwn b/openpower/isa/simplev.mdwn index d3b318ee..648f43d8 100644 --- a/openpower/isa/simplev.mdwn +++ b/openpower/isa/simplev.mdwn @@ -30,10 +30,6 @@ Pseudo-code: step <- SVSTATE_NEXT(SVi, 0b0) if _RT != 0 then GPR(_RT) <- [0]*57 || step - if Rc = 1 then - if step = 0 then c <- 0b001 - else c <- 0b010 - CR[32:35] <- c || XER[SO] else VLimm <- SVi + 1 # set or get MVL @@ -41,9 +37,7 @@ Pseudo-code: else MVL <- SVSTATE[0:6] # set or get VL if vs = 0 then VL <- SVSTATE[7:13] - else if _RA != 0 then - if (RA) >u 0b1111111 then VL <- 0b1111111 - else VL <- (RA)[57:63] + else if _RA != 0 then VL <- (RA)[57:63] else if _RT = 0 then VL <- VLimm[0:6] else if CTR >u 0b1111111 then VL <- 0b1111111 else VL <- CTR[57:63] @@ -58,10 +52,6 @@ Pseudo-code: # set requested Vertical-First mode, clear persist SVSTATE[63] <- vf SVSTATE[62] <- 0b0 - if Rc = 1 then - if VL = 0 then c <- 0b001 - else c <- 0b010 - CR[32:35] <- c || XER[SO] Special Registers Altered: diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py index f3d9d808..854d7849 100644 --- a/src/openpower/decoder/isa/caller.py +++ b/src/openpower/decoder/isa/caller.py @@ -1435,7 +1435,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers): if not self.is_svp64_mode or not pred_dst_zero: if hasattr(self.dec2.e.do, "rc"): rc_en = yield self.dec2.e.do.rc.rc - if rc_en and ins_name not in ['svstep', 'setvl']: + if rc_en and ins_name not in ['svstep']: regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0") self.handle_comparison(results, regnum) -- 2.30.2