From 6c6a9e600731146ecc236a60b7ee287863fca9e3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 May 2019 17:17:17 +0100 Subject: [PATCH] debugging score6600 matrix --- src/experiment/score6600.py | 13 ++++++++----- src/scoreboard/dependence_cell.py | 12 ++++++------ src/scoreboard/fu_reg_matrix.py | 18 +++++++++--------- 3 files changed, 23 insertions(+), 20 deletions(-) diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py index 8b3036db..d1a6d9c1 100644 --- a/src/experiment/score6600.py +++ b/src/experiment/score6600.py @@ -146,12 +146,12 @@ class Scoreboard(Elaboratable): for i, fu in enumerate(if_l): fn_issue_l.append(fu.issue_i) fn_busy_l.append(fu.busy_o) - m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i]) + m.d.comb += fu.issue_i.eq(issueunit.i.fn_issue_o[i]) m.d.comb += fu.dest_i.eq(self.int_dest_i) m.d.comb += fu.src1_i.eq(self.int_src1_i) m.d.comb += fu.src2_i.eq(self.int_src2_i) # XXX sync, so as to stop a simulation infinite loop - m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o) + m.d.sync += issueunit.i.busy_i[i].eq(fu.busy_o) fn_issue_o = Signal(len(fn_issue_l), reset_less=True) m.d.comb += fn_issue_o.eq(Cat(*fn_issue_l)) @@ -313,6 +313,9 @@ def scoreboard_sim(dut, alusim): yield dut.intregs.regs[i].reg.eq(i) alusim.setval(i, i) + yield + yield + if False: yield from int_instr(dut, alusim, IADD, 4, 3, 5) yield from print_reg(dut, [3,4,5]) @@ -343,8 +346,8 @@ def scoreboard_sim(dut, alusim): if dest not in [src1, src2]: break src1 = 3 - src2 = 4 - dest = 5 + src2 = 1 + dest = 1 op = randint(0, 1) op = 0 @@ -352,12 +355,12 @@ def scoreboard_sim(dut, alusim): yield from int_instr(dut, alusim, op, src1, src2, dest) yield from print_reg(dut, [3,4,5]) yield - yield yield from print_reg(dut, [3,4,5]) for i in range(len(dut.int_insn_i)): yield dut.int_insn_i[i].eq(0) yield yield + yield yield diff --git a/src/scoreboard/dependence_cell.py b/src/scoreboard/dependence_cell.py index 15665418..ae552077 100644 --- a/src/scoreboard/dependence_cell.py +++ b/src/scoreboard/dependence_cell.py @@ -46,14 +46,14 @@ class DependenceCell(Elaboratable): m.d.comb += src2_l.r.eq(self.go_rd_i) # FU "Forward Progress" (read out horizontally) - m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.dest_i) - m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.src1_i) - m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.src2_i) + m.d.comb += self.dest_fwd_o.eq(dest_l.q & self.go_wr_i) + m.d.comb += self.src1_fwd_o.eq(src1_l.q & self.go_rd_i) + m.d.comb += self.src2_fwd_o.eq(src2_l.q & self.go_rd_i) # Register File Select (read out vertically) - m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.go_wr_i) - m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.go_rd_i) - m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.go_rd_i) + m.d.comb += self.dest_rsel_o.eq(dest_l.q & self.dest_i) + m.d.comb += self.src1_rsel_o.eq(src1_l.q & self.src1_i) + m.d.comb += self.src2_rsel_o.eq(src2_l.q & self.src2_i) return m diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py index 1255b157..f15d19f5 100644 --- a/src/scoreboard/fu_reg_matrix.py +++ b/src/scoreboard/fu_reg_matrix.py @@ -34,8 +34,8 @@ class FURegDepMatrix(Elaboratable): self.dest_i = Signal(n_reg_col, reset_less=True) # Dest in (top) self.src1_i = Signal(n_reg_col, reset_less=True) # oper1 in (top) self.src2_i = Signal(n_reg_col, reset_less=True) # oper2 in (top) - self.issue_i = Signal(n_reg_col, reset_less=True) # Issue in (top) + self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top) self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left) self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left) @@ -146,39 +146,39 @@ class FURegDepMatrix(Elaboratable): # --- # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i # --- - for rn in range(self.n_reg_col): + for fu in range(self.n_fu_row): dest_i = [] src1_i = [] src2_i = [] - issue_i = [] - for fu in range(self.n_fu_row): + for rn in range(self.n_reg_col): dc = dm[rn][fu] # accumulate cell inputs dest/src1/src2 dest_i.append(dc.dest_i) src1_i.append(dc.src1_i) src2_i.append(dc.src2_i) - issue_i.append(dc.issue_i) # wire up inputs from module to row cell inputs (Cat is gooood) m.d.comb += [Cat(*dest_i).eq(self.dest_i), Cat(*src1_i).eq(self.src1_i), Cat(*src2_i).eq(self.src2_i), - Cat(*issue_i).eq(self.issue_i), ] # --- - # connect Dependency Matrix go_rd_i/go_wr_i to module go_rd/go_wr + # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr # --- - for fu in range(self.n_fu_row): + for rn in range(self.n_reg_col): go_rd_i = [] go_wr_i = [] - for rn in range(self.n_reg_col): + issue_i = [] + for fu in range(self.n_fu_row): dc = dm[rn][fu] # accumulate cell fwd outputs for dest/src1/src2 go_rd_i.append(dc.go_rd_i) go_wr_i.append(dc.go_wr_i) + issue_i.append(dc.issue_i) # wire up inputs from module to row cell inputs (Cat is gooood) m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i), Cat(*go_wr_i).eq(self.go_wr_i), + Cat(*issue_i).eq(self.issue_i), ] return m -- 2.30.2